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參數(shù)資料
| 型號： | XRT8001IP-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC WAN CLOCK E1/E1 DUAL 18PDIP |
| 產(chǎn)品變化通告： | XRT obsolescence 05/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 41 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)（WAN），T1/E1 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 16.384kHz |
| 電源電壓： | 3.3 V ~ 5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 18-PDIP |
| 包裝： | 管件 |
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XRT8001
26
Rev. 1.01
Step 3 – Upon reviewing Table 6, write the listed
value (under the “Value to Write to D4 – D1 in CR0”
register) into the D4 through D1 bit-fields within
Command Register CR0, as illustrated below:
Command Register CR0 (Address = 0x00)
D4
D3
D2
D1
D0
IOC4
IOC3
IOC2
IOC1
PL1EN
Value to Write to D4 – D1 in CR0
X
Notes:
1.
If the user wishes to output a clock signal via the CLK1
output signal, then he/she should also write a “1” into
the “PL1EN” bit-field within Command Register CR0.
2.
The contents of bit-fields D4 through D1 (within Com-
mand Register CR1) are “Don’t Care”
3.
If the user wishes to output a clock signal via the CLK2
output signal, then he/she should also write a “1” into
the “PL2EN” bit-field within Command Register CR1.
This step configures the XRT8001 to operate in the
“Fractional T1/E1 Reverse/Master” Mode.
Step 4 – Specify the value of “P” (e.g., as in the “P x
56kHz” or “P x 64kHz” clock signal which is to be input
via the FIN Reference Clock input).
In order to specify the value for “P”, one needs to write
in the value of “P - 1” (binary format) into Command
Register CR2, as illustrated below:
Command Register, CR2 (Address = 0x02)
D4
D3
D2
D1
D0
SEL14
SEL13
SEL12
SEL11
SEL10
Value of “P - 1” (in Binary Format).
In other words, if one intends to input either a “56kHz”
or “64kHz” clock signal via the “FIN” input pin (e.g.,
where P = 1), then he/she should write a “0” into
Command Register CR2.
Command Register, CR3 (Address = 0x03)
D4
D3
D2
D1
D0
SEL24
SEL23
SEL22
SEL21
SEL20
1
Step 6 – Enable any of the following output signals as
appropriate: “SYNC”, “CLK1”, “CLK2” and “LOCKDET”.
This is accomplished by writing a “1” into the corre-
sponding bit-fields, within Command Register CR4, as
illustrated below:
Command Register CR4, (Address = 0x04)
D4
D3
D2
D1
D0
SYNCEN
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
1
0
6.4 The “E1 to T1 –Forward/Master” Mode
When the XRT8001 WAN Clock has been configured to
operate in the “E1 to T1 – Forward/Master” Mode, then
it will accept a “Q x 2.048MHz” clock signal via the
“Reference Clock” input at FIN (pin 3), where “Q” can
range anywhere between 1 - 16. In response to this
clock signal, the XRT8001 WAN Clock will output a
1.544MHz clock signal via the Clock Output pins
(CLK1 and/or CLK2).
A simple illustration of the XRT8001 WAN Clock,
operating in the “E1 to T1 - Forward/Master” Mode is
presented in Figure 16.
Step 5 – Write the binary expression “11111” into
Command Register CR3.
This step is necessary in order to insure proper opera-
tion of the XRT8001. This step is also illustrated below:
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