參數(shù)資料
型號(hào)： XRT73L00
廠商： Exar Corporation
英文描述： E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： E3/DS3/STS-1線路接口單元
文件頁(yè)數(shù)： 11/53頁(yè)
文件大?。?/td> 604K
代理商： XRT73L00
á
XRT73L00
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.2.0
8
30
LCV/(RCLK2)
O
Line Code Violation Indicator/Receive Clock Output pin 2:
The function of this pin depends upon whether the XRT73L00 is operating in the
HOST Mode, the Hardware Mode or User selection.
HOST Mode - Line Code Violation Indicator Output:
If the XRT73L00 is configured to operate in the HOST Mode, then this pin func-
tions as the LCV output pin by default. However, by using the on-chip Command
Registers, this pin can be configured to function as the second Receive Clock
signal output pin RCLK2.
Hardware Mode - Receive Clock Output pin 2:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73L00 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
N
OTE
:
If the XRT73L00 is operating in the HOST Mode and this pin is config-
ured to function as the additional Receive Clock signal output pin, then the
XRT73L00 can be configured to update the data on the RPOS and RNEG output
pins on the falling edge of this clock signal.
31
RCLK1
O
Receive Clock Output pin 1:
This output pin is the Recovered Clock signal from the incoming line signal. The
receive section of the XRT73L00 outputs data via the RPOS and RNEG output
pins on the rising edge of this clock signal.
N
OTE
:
If the XRT73L00 is operating in the HOST Mode, the device can be con-
figured to update the data on the RPOS and RNEG output pins on the falling
edge of this clock signal.
32
RNEG
O
Receive Negative Pulse Output:
This output pin pulses “High” whenever the XRT73L00 has received a Negative
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
N
OTES
:
1. If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V")
is not reflected at this output.
2. This output pin is inactive if the XRT73L00 has been configured to oper-
ate in the Single-Rail Mode.
33
RPOS
O
Receive Positive Pulse Output:
This output pin pulses “High” whenever the XRT73L00 has received a Positive
Polarity pulse in the incoming line signal at the RTIP/RRING inputs.
N
OTE
:
If the B3ZS/HDB3 Decoder is enabled, then the zero suppression pat-
terns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not
reflected at this output.
34
ICT
I
In-Circuit Test Input:
Setting this input pin “Low” causes all digital and analog outputs to go into a
high-impedance state in order to permit in-circuit testing. Set this pin “High” for
normal operation.
N
OTE
:
This pin is internally pulled “High”.
PIN DESCRIPTION
P
IN
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YMBOL
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