Preliminary Correlated Double Sample/Hold (CDS) The function of the CDS block is to sense the voltage difference between" />
參數(shù)資料
型號： XRD98L62ACV-F
廠商： Exar Corporation
文件頁數(shù)： 9/37頁
文件大?。?/td> 0K
描述： IC CCD DIGITIZER 12BIT 48TQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 12
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
17
Rev. P2.00
XRD98L62
Preliminary
Correlated Double Sample/Hold (CDS)
The function of the CDS block is to sense the voltage
difference between the black level and video level for
each pixel. The PGA then amplifies this difference to
the desired level for the ADC. The CDS and PGA are
fully differential. The CCDin pin should be connected,
via a capacitor, to the CCD output signal. The REFin
pin should be connected, via a capacitor, to the CCD
“Common” voltage (typically the CCD ground is used
as the “Common” voltage). These capacitors, C1 and
C2, are typically 0.01
F + 10% or better matching.
The timing for the switches shown in Figure 5 are
determined by
φ1, φ2, and φ3. φ1, φ2, and φ3 are
internally generated from the timing signals SBLK and
SPIX shown in Figures 17 & 18.
φ3 (reset reject
switches) are closed to simplify the operation de-
scribed below.
At the beginning (or end) of every video line, the DC
restore switch forces one side of the external capaci-
tors to an internal bias level (Vbias1=1.2V). The DC
restore switch is controlled by the combination of the
CLAMP input signal ANDed with the
φ2 clock.
During the black reference phase of each CCD pixel the
φ1 (Sample Black Reference) switches are turned on,
shorting the PGA1 inputs to a second bias level
(Vbias2). The Coarse Offset DAC adds an adjustment
to the bias level (Vbias2) to cancel black level offset in
the CCD signal. When the
φ1 switches turn off, the
pixel black reference level is sampled on the internal
black sample capacitors, and the PGA is ready to gain
up the CCD video signal.
During the video phase of each CCD pixel the differ-
ence between the pixel black level and video level is
transmitted through the internal black sample capaci-
tors and converted to a fully differential signal by the
PGA1 amplifier. At this time the
φ2 (Sample Pixel
value) switches turn on, an the internal video sample
capacitors track the amplified difference. The Fine
Offset DAC adds offset adjustment to the PGA2 output
(post gain).
φ1
φ2
CLAMP
Vbias1=1.2V
Vbias2
REFin
CCDin
PGA1
PGA2
CCD
Coarse
Offset
DAC
PGA
CDS
External
DC Blocking
Capacitors
Internal
Black Sample
Capacitors
φ3
Internal
Video Sample
Capacitors
φ2
DC Restore Switches
C1
C2
Fine
Offset
DAC
Figure 5. CDS and PGA Block Diagram
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