Preliminary End of Line N Start of Line N+1 Active Video Pixels OB pixels Vertical Shift Dummy & OB pixels CAL Inter" />
參數(shù)資料
型號: XRD98L62ACV-F
廠商: Exar Corporation
文件頁數(shù): 26/37頁
文件大小: 0K
描述: IC CCD DIGITIZER 12BIT 48TQFP
標(biāo)準(zhǔn)包裝: 250
位數(shù): 12
通道數(shù): 1
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 2.7 V ~ 3.6 V
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
XRD98L62
32
Rev. P2.00
Preliminary
End of Line N
Start of Line N+1
Active Video
Pixels
OB pixels
Vertical Shift
Dummy &
OB pixels
CAL
Internal
DC restore time
CCD
Signal
Active Video pixels
t
CAL
4 pixels
CLAMP
(vertical shift)
Disconnect CDS from
input pins
Internal Black Level
calibration time
t
CAL - 4 pixels
Minimum 5 Pixels
Figure 22. Line Rate Timing with OneShot=1 & VSreject=1
Setting Power and Performance with Rext
The power and performance levels of the XRD98L62
are set by the value of Rext. Rext sets the current bias
level for the entire chip. Rext is connected between
pin 39 (ExtRef) and analog ground (see Figure 23).
This resistor should be placed as close as possible to
the pin and routed directly to a ground plane in a PCB
layout. A surface mount carbon resistor is recom-
mended.
Increasing values of Rext decrease the power, linearity
and noise performance of the XRD98L62. Lowering the
value of Rext increases linearity and noise perfor-
mance while increasing power. The tested default
value for Rext is 20KOhms.
In order to match system to system performance and
set consistent manufacturable performance levels
between cameras, it is recommended that the Rext
resistor have <1% tolerance.
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