Rev. 2.00 OB PIXEL CALIBRATION Line Mode Calibration In the Line mode, OB pixels are sampled when CAL is active. CAL can be program" />
參數(shù)資料
型號： XRD98L61AIV-F
廠商： Exar Corporation
文件頁數(shù)： 17/38頁
文件大小： 0K
描述： IC CCD DIGITIZER 12BIT 48TQFP
標(biāo)準(zhǔn)包裝： 250
位數(shù)： 12
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
XRD98L61
24
Rev. 2.00
OB PIXEL CALIBRATION
Line Mode Calibration
In the Line mode, OB pixels are sampled when CAL is
active. CAL can be programmed to be active high or
active low. Please see the Timing section for more
details about clock polarity. Averaging will span as
many lines as needed to get the number of OB pixels
programmed by AVG[2:0]. Updates to the offset DACs
occur during the Optical Black pixel time after a
complete iteration. A complete iteration includes the
pixel clipping, averaging, calculation of the offset dif-
ference, and calculation of the DAC update values.
After a complete iteration, the averager is reset, and
the logic waits for the number of lines programmed in
the “Wait A” & “Wait B” registers (WL[11:0]) before
starting the next iteration.
Figure 12. Clock Polarity and Aperture Delays
CLOCK BASICS
There are five clock signals: SBLK, SPIX, ADCLK,
CLAMP, and CAL.
The pixel rate clocks are SBLK, SPIX, and ADCLK.
SBLK controls sampling of the Black reference level
for each pixel. SPIX controls sampling of the Video
level for each pixel. ADCLK controls the ADC sam-
pling the PGA output.
Polarity
SBLK
SPIX
ADCLK
CAL
CLAMP
Aperture
Delays
Clock Logic
AFE
ADC
Calibration
CLOCK POLARITY
Each of the five clocks has a separate polarity control
bit in the Polarity register. If the polarity bit for a clock
is low, then the clock is active low. If the polarity bit for
a clock is high, then the clock is active high. After reset
(by POR, reset bit or reset pin), all clocks default to
active low.
Manual Mode
The purpose of this mode is to disable the automatic
calibration feature. This allows manual adjustment of
offset in applications such as digital copiers and high
speed scanners. In Manual mode, the Coarse accu-
mulator is programmed by writing to the CDAC register;
the Fine accumulator is programmed by writing to the
FDAC register. The Coarse accumulator is a 9 bit
register. The Fine accumulator is a 10 bit register.
To activate the Manual mode, write a ”1” to the ManCal
bit in the Calibration register. By default, the Manual
mode is not active.
The line rate clocks are CLAMP & CAL.
CLAMP
controls the DC restore function for the external AC
coupling capacitors.
CAL controls the Black level
calibration by defining the OB pixels at the start or end
of each line.
In the One Shot mode (CAL only),
CLAMP is used to define the vertical shift period
between lines.
相關(guān)PDF資料
PDF描述
XRD98L62ACV-F IC CCD DIGITIZER 12BIT 48TQFP
XRD98L63AIV-F IC CCD DIGITIZER 12BIT 48TQFP
XRT71D00IQ-F IC JITTER ATTENUATOR SGL 32TQFP
XRT71D03IV-F IC JITTER ATTENUATOR 3CH 64TQFP
XRT71D04IV IC JITTER ATTENUATOR 4CH 80TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRD98L61EVAL 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board for XRD98L61AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
XRD98L61ZEVAL 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board (Solder) XRD98L61AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
XRD98L62 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D
XRD98L62ACV 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D
XRD98L62ACV-F 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*