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| 型號： | XRD98L61AIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 16/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD DIGITIZER 12BIT 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.6 V |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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23
Rev. 2.00
XRD98L61
CALIBRATION OPTIONS
Fast Cal
The purpose of this option is to reduce the amount of
time required for initial convergence of the calibration
feedback system. The feedback system is designed to
have a slow response time to avoid introducing image
artifacts. The slow response time is achieved by
averaging many OB pixels and by limiting the Fine
accumulator changes to ± 1 count at a time (FDAC lsb
= ADC lsb). The FastCal option maintains this slow
response while the difference between the averaged
ADC data and the Offset Code is small, but when the
difference is larger than ±128 lsb’s, the coarse accu-
mulator takes a step. The actual step size depends on
the PGA Gain code, and is set such that the step will
cause no more than a 128 LSB change in the ADC
output.
To activate the FastCal mode ,write a “1” to the FastCal
bit in the Calibration register. By default, the FastCal
mode is active.
Difference [ADC lsb's]
O
ff
s
e
t
A
d
ju
s
tm
e
n
t
[A
D
C
L
S
B
s
]
0
-1
+1
-128
+128
0
+0.5
-0.5
Fine DAC Steps
Coarse DAC steps
Figure 11. Calibration in FastCal
(Speed Up) Mode
DNS[1]
DNS[0]
DNS Filter Width
0
OFF (default)
0
1
Narrow
1
0
Medium
1
Wide
Digital Noise Suppression (DNS Filter)
The purpose of this option is to eliminate small
changes in the Black Level offset by making the
calibration system less sensitive to small changes in
the measured offset. In this mode, the user has the
option of selecting from three filter settings;see Table 5.
Table 5. DNS Threshold Programming
To activate the Digital Noise Suppression mode, write
to the DNS[1:0] bits in the Calibration register.By
default, the Digital Noise Suppression is ON and set to
the wide filter width.
Hold Mode
The purpose of this mode is to prevent any changes in
the Fine or Coarse accumulators. This mode is in-
tended to optimize digital still camera applications
(DSC). The idea is to first run the calibration normally
so the Fine and Coarse accumulators converge on the
correct values to achieve the programmed Offset
Code. Then, just before acquiring the final image data,
activate the Hold mode. This will ensure the black level
offset of the CDS/PGA does not change while the final
image is being transferred out of the CCD. Once the
image has been acquired from the CCD, turn off the
Hold mode so the chip can continue to compensate for
any changes in offset due to temperature drift or other
effects.
To activate the Hold mode, write a “1” to the Hold bit in
the Calibration register. By default, the Hold mode is
not active.
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| XRD98L61EVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board for XRD98L61AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L61ZEVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 Eval Board (Solder) XRD98L61AIV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L62 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L62ACV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L62ACV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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