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參數(shù)資料
| 型號： | XRD9836ACG |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 9/32頁 |
| 文件大小： | 0K |
| 描述： | IC 16B CCD/CIS SIG PROC 48TSSOP |
| 產(chǎn)品變化通告： | Leaded UART, V&I Obsolescence 11/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 500mW |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 封裝/外殼： | 48-TSSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
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xr
xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
17
MICRO-CONTROLLER SERIAL PORT
FOR MODE CONTROL (USIO):
The uSIO is a bidirectional I/O port which is used for
configuring various operating modes as well as phase
aligning internal clocks (delay control). The serial port
can be used to program any of the registers listed in
the registers table. Note that SDIO is a bidirectional
pin used to read or write the XRD9836 internal regis-
ters. The R/W bit will define the direction of the bus
after Address bits. If R/W = 0, a write to the XRD9836
is performed. If R/W = 1, a read of the XRD9836’s in-
ternal registers is performed.
During a write operation there must be 18 positive
edges of SCLK between the fall of LOAD and the rise
of LOAD. If there are more or less than 18, the write
operation will not take place. For a write to the
XRD9836 the SDIO pin stays configured as an input
for entire 18 SCLK's before LOAD goes high. The E0
and E1 bits are dummy (unused) bits.
For a read of the XRD9836 internal registers (R/W=1)
the E0 and E1 are used as a transition time for the
SDIO pin going from an input to a output. During this
time SDIO pin is tri-stated. SDIO is an input while se-
rial port accepts the address of the register to be read
and during the E0 and E1 time period transitions to
an output for the read operation.
During a read operation the first 18 positive edges are
used. If there are less than 18, not all of the data will
be output. If there are more than 18, only the first 18
bits will be valid. The data becomes valid after the ris-
ing edge of SCLK.
FIGURE 15. SERIAL PORT WRITE TIMING (R/W=0)
A3
A2
A1
A0
A4
D7
D6
D5
D4
D3
D2
D1
D0
D8
D9
R/W
E0
E1
msb
lsb
LOAD
SCLK
SDIO
Tusp
Tuss
Tusls
Tuslh
Write
Register Address
Dummy
bits
Write Register Data
SDIO
configured
as
Input
Tush
FIGURE 16. SERIAL PORT READ TIMING (R/W=1)
A3
A2
A1
A0
A4
D7
D6
D5
D4
D3
D2
D1
D0
D8
D9
R/W
E0
E1
msb
lsb
LOAD
SCLK
SDIO
Tusp
Tuss
Tusdvd
Tusls
Tuslh
Read
Register Address
Dummy
bits
Read Register Data
SDIO
configured
as
Input
Tri-state
Output
Tush
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