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參數(shù)資料
| 型號： | XRD9836ACG |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 16B CCD/CIS SIG PROC 48TSSOP |
| 產(chǎn)品變化通告： | Leaded UART, V&I Obsolescence 11/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 500mW |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 封裝/外殼： | 48-TSSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
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xr
xr
XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
23
Control / Polarity
Register
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CNTRL / POL
(01111)
ADC
POL
LCLMP
POL
BSAMP
POL
VSAMP
POL
DLP
DISABLE
PWRDWN
OEB
RESET
default
0
The CNTRL / POL register is used to program various options including: input timing polarity control, dynamic low
power disable, power down for the chip, output enable, and reset. Reset will reset ALL registers including reset.
All the clock inputs (except the serial interface SCLK) can be programmed to be active high or active low. See the “Tim-
ing” section for more information. ADCpol, LCLMPpol, BSAMPpol, and VSAMPpol set the polarity of ADCLK, LCLMP,
BSAMP, and VSAMP respectively.
ADCpol - Sets the polarity of the ADCLK input. ADCpol = 0, ADCLK low during VSAMP. ADCpol = 0, ADCLK inverted
so that it is high during VSAMP.
LCLMPpol - Sets the polarity of the LCLMP input. LCLMPpol = 0, LCMLP is active high during clamping operation and
odd pixel determined from falling edge.
BSAMPpol - Sets the polarity of the BSAMP input. BSAMPpol = 0, BSAMP is active high. The CCD black level is sam-
ple by the falling edge. BSAMPpol = 1, BSAMP is active low. The CCD black level is sample by the rising edge.
VSAMPpol - Sets the polarity of the VSAMP input. VSAMPpol = 0, VSAMP is active high. The CCD video level is sam-
ple by the falling edge. VSAMPpol = 1, VSAMP is active low. The CCD video level is sample by the rising edge.
DLP DISABLE (ADC Dynamic Low Power Disable)
PWRDWN - Puts the XRD9836 into power down state. PWRDWN = 0, normal operation. PWRDWN = 1, low power
state.
OEB - Enables the ADCDO bus. OEB = 0, data valid on ADCDO bus. OEB = 1, ADCDO bus high impedance.
RESET - Will reset the XRD9836 to default (power up) conditions. RESET = 0, normal operation. RESET = 1, all inter-
nal registers set to default values and clears itself after ~ 10ns.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XRD9836ACG-F | 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| XRD9836ACGTR-F | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| XRD9853AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA, and 10-bit A/D |
| XRD9855 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 10-Bit A/D |
| XRD9855AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 10-Bit A/D |
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