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參數(shù)資料
| 型號： | XRD9818ACGTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 0K |
| 描述： | IC 16B CCD/CIS SIG PROC 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 325mW |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
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xr
XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
17
4.1.2
Clamp/Reference (C/R) DAC
4.1.2.1
Clamp Operation in CCD Mode
In CCD mode a clamp is required to level shift the CCD output signal into XRD9818’s input common mode
range. The clamp circuitry ensures that the signals present at the analog inputs fall within the operating range
of those pins. The clamp operation takes place while BSAMP is active. When BSAMP is active, SW1 is closed
connecting the C/R DAC to the analog input pin.
This establishes the C/R DAC voltage on the external
coupling cap. When SW1 is opened, the C/R DAC voltage is stored on the external coupling cap. This clamping
operation will occur while BSAMP is active. The C/R DAC clamp voltage is programmable. This gives the
system designer added flexibility to make adjustments for different sensor signal swing and reset pulse
characteristics.
The XRD9818 has 2 clamp modes available for used in CCD applications, Line Clamp and Pixel Clamp.
Line Clamp mode only performs the clamp when the LCLMP pin is active.
The control timing,
φ
CL, for SW1 is
generated by the “ANDing” of the external timing signals LCLMP & BSAMP and is shown in Figure 6.
FIGURE 5. CCD MODE INPUT CLAMP (ALL THREE CHANNELS ARE IDENTICAL)
FIGURE 6. LINE CLAMP MODE TIMING
φ
R
φ
R
φ
CL
C/R DAC
to PGA
CMN-
RED+
CL[2]
CL[1]
CL[0]
C1
C2
Clamp/Reference DAC
SW1
SW2
SW3
0.1uf
CCD
ouput
C
IN
C
REF
1nf
RED+
CCD
IN
ADCLK
BSAMP
VSAMP
φ
CL
LCLMP
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