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參數(shù)資料
| 型號： | XRD9818ACGTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 16B CCD/CIS SIG PROC 28TSSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 325mW |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
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XRD9818
xr
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
18
Pixel Clamp mode eliminates the gating function of BSAMP with LCLMP.
In Pixel Clamp mode the clamping
function is performed with every BSAMP, see Figure 7. Selection of the Line Clamp or Pixel Clamp modes is
defined by the state of the LC bit (D5) located in the MODE 1 register.
4.1.2.2
Reference Operation in CIS Mode
In most CIS applications the imager output is connected directly to the inputs. With no external coupling
capacitor, there is no need to perform a clamp. Unlike a CCD output signal that has a black reference level for
each pixel a CIS output is sampled with respect to a black reference voltage. In CIS mode, the C/R DAC is
used to provide that reference as shown below in Figure 8.
The reference voltage is programmable to help
interface to a variety of CIS imagers.
If a CIS imager provides its own reference voltage the C/R DAC can be configured into a "high Z" state so that
an external reference can be connected directly to the CMN- pin. See the MODE 1 Register definition of bits
C/R[2:0].
FIGURE 7. PIXEL CLAMP MODE TIMING
FIGURE 8. CIS MODE REFERENCE (INTERNAL OR EXTERNAL)
CCD
IN
ADCLK
BSAMP
VSAMP
φ
CL
C/R DAC
to PGA
CMN-
CL[2]
CL[1]
CL[0]
C1
C2
Clamp/Reference DAC
0.1uf
CIS
Signal
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