REV. 1.4.3 5V PCI BUS OCTAL UART 3 PIN DESCRIPTIONS Pin Description NAME
參數(shù)資料
型號: XR17C158CV-0A-EVB
廠商: Exar Corporation
文件頁數(shù): 23/67頁
文件大小: 0K
描述: EVAL BOARD FOR XR17C158-A 144TQF
標(biāo)準(zhǔn)包裝: 1
系列: *
xr
XR17C158
REV. 1.4.3
5V PCI BUS OCTAL UART
3
PIN DESCRIPTIONS
Pin Description
NAME
PIN #
TYPE
DESCRIPTION
PCI LOCAL BUS INTERFACE
RST#
134
I
Bus reset input (active low). It resets the PCI local bus configuration space
registers, device configuration registers and UART channel registers to the
default condition, see Table 19.
CLK
135
I
Bus clock input of up to 33.34MHz at 5V.
AD31-AD25,
AD24,
AD23-AD16,
AD15-AD8,
AD7-AD0
138-144,
1,
6-13,
26-33,
37-44
IO
Address data lines [31:0] (bidirectional).
FRAME#
15
I
Bus transaction cycle frame (active low). It indicates the beginning and dura-
tion of an access.
C/BE0#-C/BE3#
36,25,14,2
I
Bus Command/Byte Enable [3:0] (active low). This line is multiplexed for bus
Command during the address phase and Byte Enables during the data phase.
IRDY#
16
I
Initiator Ready (active low). During a write, it indicates that valid data is
present on data bus. During a read, it indicates the master is ready to accept
data.
TRDY#
17
O
Target Ready (active low).
STOP#
21
O
Target request to stop current transaction (active low).
IDSEL
3
I
Initialization device select (active high).
DEVSEL#
18
O
Device select to the XR17C158 (active low).
INTA#
133
OD
Device interrupt from XR17C158 (open drain, active low).
PAR
24
IO
Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active high).
PERR#
22
O
Data Parity error indicator, except for Special Cycle transactions (active low).
Optional in bus target application.
SERR#
23
OD
System error indicator, Address parity or Data parity during Special Cycle
transactions (open drain, active low). Optional in bus target application.
MODEM OR SERIAL I/O INTERFACE
TX0
125
O
UART channel 0 Transmit Data or infrared transmit data.
RX0
132
I
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles HIGH. The infrared pulses typically idle LOW but can be inverted inter-
nally prior the decoder by FCTR[4].
RTS0#
127
O
UART channel 0 Request to Send or general purpose output (active low).
CTS0#
131
I
UART channel 0 Clear to Send or general purpose input (active low).
DTR0#
126
O
UART channel 0 Data Terminal Ready or general purpose output (active low).
DSR0#
130
I
UART channel 0 Data Set Ready or general purpose input (active low).
CD0#
129
I
UART channel 0 Carrier Detect or general purpose input (active low).
RI0#
128
I
UART channel 0 Ring Indicator or general purpose input (active low).
TX1
117
O
UART channel 1 Transmit Data or infrared transmit data.
RX1
124
I
UART channel 1 Receive Data or infrared receive data. Normal RXD input
idles HIGH. The infrared pulses can be inverted internally prior the decoder by
FCTR[4].
RTS1#
119
O
UART channel 1 Request to Send or general purpose output (active low).
CTS1#
123
I
UART channel 1 Clear to Send or general purpose input (active low).
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XR17C158IV-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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