參數(shù)資料
型號： XR17C152CM-F
廠商： Exar Corporation
文件頁數(shù)： 35/62頁
文件大?。?/td> 0K
描述： IC UART PCI BUS DUAL 100TQFP
標準包裝： 90
特點： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
XR17C152
á
5V PCI BUS DUAL UART
REV. 1.2.0
40
LCR[6]: Transmit Break Enable
When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.8.8
Modem Control Register (MCR) - Read/Write
The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Pins
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the
modem interface is not used, this output may be used for general purpose.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Pins
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit-2=0. If
the modem interface is not used, this output may be used for general purpose.
Logic 0 = Force RTS# output HIGH (default).
Logic 1 = Force RTS# output LOW.
MCR[2]: DTR# or RTS# for Auto Flow Control
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by
EFR bit-6. DTR# selection is associated with DSR# and RTS# is with CTS#.
Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control.
Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control.
MCR[3]: (OP2)
The OP2 output is not available in the XR17C152.
It is present for 16C550 compatibility during internal
loopback. See Figure 16. Logic 0 is default.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable internal loopback mode (default).
Logic 1 = Enable internal loopback mode, see loopback section and Figure 16.
TABLE 15: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
XX
0
No parity
0
1
Odd parity
01
1
Even parity
1
0
1
Force parity to mark, “1”
1
Forced parity to space, “0”
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