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參數(shù)資料
| 型號： | XR16C850IM |
| 英文描述： | UART|CMOS|TQFP|48PIN|PLASTIC |
| 中文描述： | 異步|的CMOS | TQFP封裝| 48PIN |塑料 |
| 文件頁數(shù)： | 29/49頁 |
| 文件大?。?/td> | 690K |
| 代理商： | XR16C850IM |
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XR16C854/XR16C854D
3.3V AND 5V QUAD UART WITH 128-BYTE FIFO
REV. 2.0
29
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be
used for automatic hardware flow control by enabled
by EFR bit-6. If the modem interface is not used, this
output may be used as a general purpose output.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the 854.
But it is available for use during Internal Loopback
Mode. In the Loopback Mode, this bit is used to write
the state of the modem RI# interface signal. If OP1#
output is required for RS485 operation, use the
XR16C864.
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in
three-state. This function is associated with the INT-
SEL input, see below table for details. This bit is also
used to control the OP2# signal during internal loop-
back mode. INTSEL pin must be set to a logic zero
during 68 mode.
Logic 0 = INT (A-D) outputs disabled (three state) in
the 16 mode (default). During loopback mode, it
sets OP2# internally to a logic 1.
Logic 1 = INT (A-D) outputs enabled (active) in the
16 mode. During loopback mode, it sets OP2#
internally to a logic 0.
T
ABLE
13: INT O
UTPUT
M
ODES
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loop-
back section and Figure 13.
MCR[5]: Xon-Any Enable
Logic 0 = Disable Xon-Any function (for 16C550
compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode,
any RX character received will resume transmit
operation. The RX character will be loaded into the
RX FIFO , unless the RX character is an Xon or
Xoff character and the 854 is programmed to use
the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 = Enable the standard modem receive and
transmit input/output interface. (Default)
Logic 1 = Enable infrared IrDA receive and transmit
inputs/outputs. The TX/RX output/input are routed
to the infrared encoder/decoder. The data input and
output levels conform to the IrDA infrared interface
requirement. The RX FIFO may need to be flushed
upon enable. While in this mode, the infrared TX
output will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
Logic 0 = Divide by one. The input clock from the
crystal or external clock is fed directly to the Pro-
grammable Baud Rate Generator without further
modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the
input clock from the crystal or external clock by four
and feeds it to the Programmable Baud Rate Gen-
erator, hence, data rates become one forth.
4.8
L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
This register provides the status of data transfers be-
tween the UART and the host. If LSR bits 1-4 are as-
serted, an interrupt will be generated immediately if
IER bit-2 is enabled.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or
FIFO (default).
Logic 1 = Data has been received and is saved in
the receive holding register or FIFO.
LSR[1]: Receiver Overrun Flag
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condi-
tion occurred in the receive shift register. This hap-
pens when additional data arrives while the FIFO is
full. In this case the previous data in the receive
shift register is overwritten. Note that under this
condition the data byte in the receive shift register
is not transferred into the FIFO, therefore the data
in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR
does not have correct parity information and is sus-
pect. This error is associated with the character
available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
Logic 0 = No framing error (default).
INTSEL
P
IN
MCR
B
IT
-3
INT A-D O
UTPUTS
IN
16 M
ODE
0
0
Three-State
0
1
Active
1
X
Active
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| XR16C850IP | UART|CMOS|DIP|40PIN|PLASTIC |
| XR16C850IQ | UART|CMOS|QFP|52PIN|PLASTIC |
| XR17C158CV | UART |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C850IM-F | 功能描述:UART 接口集成電路 UARTW/128BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C850IMTR-F | 功能描述:UART 接口集成電路 UART W/128 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C850IP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART|CMOS|DIP|40PIN|PLASTIC |
| XR16C850IQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART|CMOS|QFP|52PIN|PLASTIC |
| XR16C854 | 制造商:EXAR 制造商全稱:EXAR 功能描述:并轉(zhuǎn)串4串口擴(kuò)展芯片 |
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