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參數(shù)資料
| 型號： | XR16C850IJ |
| 英文描述： | UART|CMOS|LDCC|44PIN|PLASTIC |
| 中文描述： | 異步|的CMOS | LDCC | 44PIN |塑料 |
| 文件頁數(shù)： | 5/49頁 |
| 文件大小： | 690K |
| 代理商： | XR16C850IJ |
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XR16C854/XR16C854D
3.3V AND 5V QUAD UART WITH 128-BYTE FIFO
REV. 2.0
5
PIN DESCRIPTIONS
Pin Description
N
AME
64-TQFP
P
IN
#
68-PLCC
P
IN
#
100-QFP
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(VCC)
22
23
24
60
59
58
57
56
55
54
53
40
32
33
34
5
4
3
2
1
68
67
66
52
37
38
39
95
94
93
92
91
90
89
88
66
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A-D during a data bus transaction.
I/O
Data bus lines [7:0] (bidirectional).
I
When 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an inter-
nal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising
edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input is not used and should be connected to VCC.
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte on
the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is at logic 1, this input is chip select A (active low) to
enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select
(active low) for the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is at logic 1, this input is chip select B (active low) to
enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is at logic 1, this input is chip select C (active low) to
enable channel C in the device.
When 16/68# pin is at logic 0, this input becomes address line A4
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is at logic 1, this input is chip select D (active low) to
enable channel D in the device.
When 16/68# pin is at logic 0, this input is not used and should be
connected VCC.
Motorola bus interface is not available on the 64 pin package.
IOW#
(R/W#)
9
18
15
I
CSA#
(CS#)
7
16
13
I
CSB#
(A3)
11
20
17
I
CSC#
(A4)
38
50
64
I
CSD#
(VCC)
42
54
68
I
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C850IJ-F | 功能描述:UART 接口集成電路 UARTW/128BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C850IJTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC T/R |
| XR16C850IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C850IM-F | 功能描述:UART 接口集成電路 UARTW/128BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C850IMTR-F | 功能描述:UART 接口集成電路 UART W/128 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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