參數(shù)資料
型號: XR16C850IJ
英文描述: UART|CMOS|LDCC|44PIN|PLASTIC
中文描述: 異步|的CMOS | LDCC | 44PIN |塑料
文件頁數(shù): 49/49頁
文件大?。?/td> 690K
代理商: XR16C850IJ
á
XR16C854/XR16C854D
3.3V AND 5V QUAD UART WITH 128-BYTE FIFO
REV. 2.0
II
4.3 I
NTERRUPT
E
NABLE
R
EGISTER
(IER) - R
EAD
/W
RITE
.......................................................................... 24
4.3.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................................... 24
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 25
4.4 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) - R
EAD
-O
NLY
............................................................................ 25
4.4.1 Interrupt Generation:................................................................................................................................ 25
4.4.2 Interrupt Clearing: .................................................................................................................................... 26
T
ABLE
10: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
............................................................................................................................. 26
4.5 FIFO C
ONTROL
R
EGISTER
(FCR) - W
RITE
-O
NLY
............................................................................... 26
T
ABLE
11: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
................................................................................................... 27
4.6 L
INE
C
ONTROL
R
EGISTER
(LCR) - R
EAD
/W
RITE
................................................................................ 28
4.7 M
ODEM
C
ONTROL
R
EGISTER
(MCR)
OR
G
ENERAL
P
URPOSE
O
UTPUTS
C
ONTROL
- R
EAD
/W
RITE
....... 28
T
ABLE
12: P
ARITY
SELECTION
................................................................................................................................................................ 28
T
ABLE
13: INT O
UTPUT
M
ODES
............................................................................................................................................................ 29
4.8 L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
..................................................................................... 29
4.9 M
ODEM
S
TATUS
R
EGISTER
(MSR) - R
EAD
O
NLY
............................................................................... 30
4.10 S
CRATCH
P
AD
R
EGISTER
(SPR) - R
EAD
/W
RITE
............................................................................... 30
4.11 E
NHANCED
M
ODE
S
ELECT
R
EGISTER
(EMSR) ................................................................................. 31
T
ABLE
14: S
CRATCHPAD
S
WAP
S
ELECTION
............................................................................................................................................ 31
4.12 FIFO L
EVEL
R
EGISTER
(FLVL) - R
EAD
-O
NLY
.................................................................................. 31
4.13 B
AUD
R
ATE
G
ENERATOR
R
EGISTERS
(DLL
AND
DLM) - R
EAD
/W
RITE
.............................................. 31
4.14 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
................................................................. 31
4.15 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
......................................................................... 31
T
ABLE
15: A
UTO
RTS H
YSTERESIS
....................................................................................................................................................... 31
4.16 T
RIGGER
L
EVEL
(TRG) - W
RITE
-O
NLY
............................................................................................ 32
4.17 FIFO D
ATA
C
OUNT
R
EGISTER
(FC) - R
EAD
-O
NLY
........................................................................... 32
4.18 F
EATURE
C
ONTROL
R
EGISTER
(FCTR) - R
EAD
/W
RITE
.................................................................... 32
4.19 E
NHANCED
F
EATURE
R
EGISTER
(EFR) - R
EAD
/W
RITE
..................................................................... 32
T
ABLE
16: T
RIGGER
T
ABLE
S
ELECT
....................................................................................................................................................... 32
T
ABLE
17: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
............................................................................................................................... 33
4.20 S
OFTWARE
F
LOW
C
ONTROL
R
EGISTERS
(XOFF1, XOFF2, XON1, XON2) - R
EAD
/W
RITE
............... 34
4.21 FIFO S
TATUS
R
EGISTER
(FSTAT) - R
EAD
/W
RITE
........................................................................... 34
T
ABLE
18: UART RESET CONDITIONS FOR CHANNELS A-D......................................................................................................... 34
ABSOLUTE MAXIMUM RATINGS ..................................................................................35
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)35
ELECTRICAL CHARACTERISTICS................................................................................35
DC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................35
AC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................36
TA=0
O
TO
70
O
C (-40
O
TO
+85
O
C
FOR
INDUSTRIAL
GRADE
PACKAGE
), V
CC
IS
3.3- 5.0V ±10%.................36
F
IGURE
14. C
LOCK
T
IMING
.................................................................................................................................................................... 37
F
IGURE
15. M
ODEM
I
NPUT
/O
UTPUT
T
IMING
F
OR
C
HANNELS
A-D............................................................................................................ 38
F
IGURE
16. 16 M
ODE
(I
NTEL
) D
ATA
B
US
R
EAD
T
IMING
FOR
C
HANNELS
A-D........................................................................................... 38
F
IGURE
17. 16 M
ODE
(I
NTEL
) D
ATA
B
US
W
RITE
T
IMING
FOR
C
HANNELS
A-D ......................................................................................... 39
F
IGURE
18. 68 M
ODE
(M
OTOROLA
) D
ATA
B
US
R
EAD
T
IMING
FOR
C
HANNELS
A-D .................................................................................. 39
F
IGURE
19. 68 M
ODE
(M
OTOROLA
) D
ATA
B
US
W
RITE
T
IMING
FOR
C
HANNELS
A-D................................................................................. 40
F
IGURE
20. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A-D.................................................................... 40
F
IGURE
21. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A-D.................................................................. 41
F
IGURE
22. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA D
ISABLED
]
FOR
C
HANNELS
A-D.................................................. 41
F
IGURE
23. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA E
NABLED
]
FOR
C
HANNELS
A-D................................................... 42
F
IGURE
24. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
]
FOR
C
HANNELS
A-D...................................... 42
F
IGURE
25. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
E
NABLED
]
FOR
C
HANNELS
A-D....................................... 43
P
ACKAGE
D
IMENSIONS
..............................................................................................................................44
R
EVISION
H
ISTORY
....................................................................................................................................47
TABLE OF CONTENTS ................................................................................................................................. I
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