參數(shù)資料
型號： XR-1790
英文描述： Audio Schematic
中文描述： 音頻示意圖
文件頁數(shù)： 57/58頁
文件大?。?/td> 676K
代理商： XR-1790
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.0.0
á
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
A
PPLICATIONS
................................................................................................................................................1
F
EATURES
.....................................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
............................................................................................................................................................. 1
F
IGURE
2. P
IN
O
UT
OF
THE
D
EVICE
.................................................................................................................................................. 2
ORDERING
INFORMATION
.................................................................................................................................2
PIN DESCRIPTIONS ..........................................................................................................3
PCI LOCAL BUS INTERFACE.....................................................................................................................3
MODEM OR SERIAL I/O INTERFACE........................................................................................................3
ANCILLARY SIGNALS.................................................................................................................................4
FUNCTIONAL DESCRIPTION ...........................................................................................6
PCI Local Bus Interface...............................................................................................................................................6
PCI Local Bus Configuration Space
Registers............................................................................................................6
EEPROM Interface......................................................................................................................................................6
1.0 XR17L154 REGISTERS .........................................................................................................................7
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................ 7
F
IGURE
3. T
HE
XR17L154 R
EGISTER
S
ETS
..................................................................................................................................... 7
T
ABLE
1: PCI L
OCAL
B
US
C
ONFIGURATION
S
PACE
R
EGISTERS
......................................................................................................... 8
1.2 DEVICE CONFIGURATION REGISTER SET ................................................................................................... 9
T
ABLE
2: XR17L154 D
EVICE
C
ONFIGURATION
R
EGISTERS
............................................................................................................. 10
T
ABLE
3: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
BYTE
ALIGNMENT
................................................................................... 11
1.2.1 THE INTERRUPT STATUS REGISTER ..................................................................................................................... 12
T
ABLE
4: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
DWORD
ALIGNMENT
............................................................................... 12
F
IGURE
4. T
HE
G
LOBAL
I
NTERRUPT
R
EGISTER
, INT0, INT1, INT2
AND
INT3.................................................................................. 13
T
ABLE
5: UART C
HANNEL
[3:0] I
NTERRUPT
S
OURCE
E
NCODING
..................................................................................................... 13
1.2.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-
00-00).............................................................................................................................................................................. 14
T
ABLE
6: UART C
HANNEL
[3:0] I
NTERRUPT
C
LEARING
: .................................................................................................................. 14
F
IGURE
5. T
IMER
/C
OUNTER
CIRCUIT
............................................................................................................................................... 14
T
ABLE
7: TIMER CONTROL R
EGISTERS
...................................................................................................................................... 14
1.2.3 8XMODE [7:0] - (DEFAULT 0X00) ............................................................................................................................. 15
1.2.4 REGA [15:8] - (DEFAULT 0X00) ................................................................................................................................ 15
1.2.5 RESET [23:16] - (DEFAULT 0X00)............................................................................................................................. 15
1.2.6 SLEEP [31:24] - (DEFAULT 0X00)............................................................................................................................ 16
1.2.7 DEVICE IDENTIFICATION AND REVISION............................................................................................................... 16
1.2.8 RGEB REGISTER ....................................................................................................................................................... 16
1.2.9 MULTI-PURPOSE INPUTS AND OUTPUTS.............................................................................................................. 17
1.2.10 MPIO REGISTER ...................................................................................................................................................... 17
F
IGURE
6. M
ULTIPURPOSE
INPUT
/
OUTPUT
INTERNAL
CIRCUIT
........................................................................................................... 17
2.0 CRYSTAL OSCILLATOR / BUFFER ...................................................................................................19
3.0 TRANSMIT AND RECEIVE DATA .......................................................................................................19
F
IGURE
7. T
YPICAL
OSCILLATOR
CONNECTIONS
............................................................................................................................... 19
3.1 FIFO
DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS IN 32-BIT
FORMAT. ........................................................................................................................................................ 20
3.2 FIFO
DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN
8-BIT FORMAT. .............................................................................................................................................. 21
4.0 UART ....................................................................................................................................................21
T
ABLE
8: T
RANSMIT
AND
R
ECEIVE
D
ATA
R
EGISTER
IN
B
YTE
FORMAT
, 16C550
COMPATIBLE
............................................................ 21
4.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 22
F
IGURE
8. B
AUD
R
ATE
G
ENERATOR
............................................................................................................................................... 22
4.2 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION .............................. 23
T
ABLE
9: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
AT
16X S
AMPLING
.......................................... 23
F
IGURE
9. A
UTO
RTS/DTR
AND
CTS/DSR F
LOW
C
ONTROL
O
PERATION
........................................................................................ 24
4.3 INFRARED MODE .......................................................................................................................................... 25
F
IGURE
10. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
.......................................................................... 25
4.4 INTERNAL LOOPBACK ................................................................................................................................. 26
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ...................................... 26
F
IGURE
11. I
NTERNAL
L
OOP
B
ACK
................................................................................................................................................. 26
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