參數(shù)資料
型號： XR-1790
英文描述： Audio Schematic
中文描述： 音頻示意圖
文件頁數(shù)： 12/58頁
文件大?。?/td> 676K
代理商： XR-1790
á
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.0.0
12
1.2.1
The XR17L154 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is a 4-bit indicator in INT0 register representing the 4
channels with the first 4 bits representing each channel from 0 to 3. This permits the interrupt routine to quickly
vector and serve that UART channel and determine the source(s) in each individual routines. INT0 bit-0
represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or modem port
status requires service. Other bits in the INT0 register provide indication for the other channels with bit-3
representing UART channel 4 respectively, bits 4 to 7 are reserved and remain at logic zero.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1 and INT2 registers provide the 12-bit interrupt status
for all 4 channels. Bits 8, 9 and 10 representing channel 0 and bits 17,18 and 19 representing channel 3
respectively. Bits 20 to 31 are reserved and remain at logic zero. All 4 channel interrupts status are available
with a single DWORD read operation. This feature allows the
host quickly vectors and serves the interrupts,
reducing service interval, hence, reduce host bandwidth requirement.
The Interrupt Status Register
All bits start up zero. A special interrupt condition is generated by the L154 upon awakening from sleep after all
4 channels were put to sleep mode earlier.
Figure 4
shows the 4-byte interrupt register and its make up.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-3
indicates channel 3. Logic one indicates the channel N [3:0] has called for service. Bits 4 to 7 are reserved and
remain at logic zero The interrupt bit clears after reading the appropriate register of the interrupting channel
register, see Interrupt Clearing section.
T
ABLE
4: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
DWORD
ALIGNMENT
A
DDRESS
R
EGISTER
B
YTE
3 [31:24]
B
YTE
2 [23:16]
B
YTE
1 [15:8]
B
YTE
0 [7:0]
0x080
-
083
INTERRUPT (read-only)
INT3
INT2
INT1
INT0
0x084-087
TIMER (read/write)
TIMERMSB
TIMERLSB
TIMER
(reserved)
TIMERCNTL
0x088-08B
ANCILLARY1 (read/write)
SLEEP
RESET
REGA
(reserved)
8XMODE
0x08C-08F
ANCILLARY2 (read-only)
MPIOINT
REGB
DVID
DREV
0x090-093
MPIO (read/write)
MPIOSEL
MPIOINV
MPIO3T
MPIOLVL
GLOBAL INTERRUPT REGISTER (DWORD) - [default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
INT0 register provides status for each channel
INT0 Register
Individual UART Channel Interrupt Status
Rsvd
Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Rsvd Rsvd Rsvd
相關PDF資料
PDF描述
XR17L154CV Telecomm/Datacomm
XR17L154IV Telecomm/Datacomm
XR-2011CN Septuple Peripheral Driver
XR-2012CN Septuple Peripheral Driver
XR-2013CN Septuple Peripheral Driver
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