參數(shù)資料
型號(hào)： XR-1790
英文描述： Audio Schematic
中文描述： 音頻示意圖
文件頁(yè)數(shù)： 35/58頁(yè)
文件大?。?/td> 676K
代理商： XR-1790
XR17L154
3.3V PCI BUS QUAD UART
REV. 1.0.0
á
35
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software.
Logic 0 = Set DMA to mode 0. (default)
Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
The FCTR Bits 6-7 are associated with these 2 bits by selecting one of the four tables. The 4 user selectable
trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO
falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the
trigger level on last re-load.
Table 13
below shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the
receiver FIFO interrupt.
Table 13
shows the complete selections.
相關(guān)PDF資料
PDF描述
XR17L154CV Telecomm/Datacomm
XR17L154IV Telecomm/Datacomm
XR-2011CN Septuple Peripheral Driver
XR-2012CN Septuple Peripheral Driver
XR-2013CN Septuple Peripheral Driver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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