參數(shù)資料
型號: XPC850SRZT80B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Communications Controller Hardware Specifications
中文描述: 32-BIT, 80 MHz, RISC PROCESSOR, PBGA256
封裝: PLASTIC, BGA-256
文件頁數(shù): 30/68頁
文件大?。?/td> 384K
代理商: XPC850SRZT80B
30
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA
Layout Practices
Figure 20 provides the timing for the asynchronous external master memory access controlled by the
GPCM.
Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 21 provides the timing for the asynchronous external master control signals negation.
Figure 21. Asynchronous External Master—Control Signals Negation Timing
Table 7 provides interrupt timing for the MPC850.
Table 7. Interrupt Timing
Num
Characteristic
1
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no
direct relation with the total system interrupt latency that the MPC850 is able to support
50 MHz
66MHz
80 MHz
Unit
Min
Max
Min
Max
Min
Max
I39
IRQx valid to CLKOUT rising edge (set up time)
6.00
6.00
6.00
ns
I40
IRQx hold time after CLKOUT.
2.00
2.00
2.00
ns
I41
IRQx pulse width low
3.00
3.00
3.00
ns
I42
IRQx pulse width high
3.00
3.00
3.00
ns
I43
IRQx edge-to-edge time
80.00
121.0
100.0
ns
CLKOUT
AS
A[6:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
AS
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
B43
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XPC850ZT50B 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Communications Controller Hardware Specifications