參數(shù)資料
型號： XPC850SRZT80B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： Communications Controller Hardware Specifications
中文描述： 32-BIT, 80 MHz, RISC PROCESSOR, PBGA256
封裝： PLASTIC, BGA-256
文件頁數(shù)： 17/68頁
文件大?。?/td> 384K
代理商： XPC850SRZT80B
MOTOROLA
MPC850 (Rev. A/B/C) Hardware Specifications
17
Layout Practices
B37
UPWAIT valid to CLKOUT falling
edge
10
6.00
—
6.00
—
6.00
—
—
50.00
ns
B38
CLKOUT falling edge to UPWAIT
valid
10
1.00
—
1.00
—
1.00
—
—
50.00
ns
B39
AS valid to CLKOUT rising edge
11
7.00
—
7.00
—
7.00
—
—
50.00
ns
B40
A[6–31], TSIZ[0–1], RD/WR,
BURST, valid to CLKOUT rising
edge.
7.00
—
7.00
—
7.00
—
—
50.00
ns
B41
TS valid to CLKOUT rising edge
(setup time)
7.00
—
7.00
—
7.00
—
—
50.00
ns
B42
CLKOUT rising edge to TS valid
(hold time)
2.00
—
2.00
—
2.00
—
—
50.00
ns
B43
AS negation to memory
controller signals negation
—
TBD
—
TBD
TBD
—
—
50.00
ns
1
The minima provided assume a 0 pF load, whereas maxima assume a 50pF load. For frequencies not marked on the
part, new bus timing must be calculated for all frequency-dependent AC parameters. Frequency-dependent AC
parameters are those with an entry in the FFactor column. AC parameters without an FFactor entry do not need to be
calculated and can be taken directly from the frequency column corresponding to the frequency marked on the part.
The following equations should be used in these calculations.
For a frequency F, the following equations should be applied to each one of the above parameters:
For minima:
For maxima:
where:
D is the parameter value to the frequency required in ns
F is the operation frequency in MHz
D
50
is the parameter value defined for 50 MHz
CAP LOAD is the capacitance load on the signal in question.
FFACTOR is the one defined for each of the parameters in the table.
2
Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value.
3
If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum
values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
4
The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter. The timing for BG
output is relevant when the MPC850 is selected to work with internal bus arbiter.
5
The setup times required for TA, TEA, and BI are relevant only when they are supplied by an external device (and not
when the memory controller or the PCMCIA interface drives them).
6
The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter. The
timing for BG input is relevant when the MPC850 is selected to work with the external bus arbiter.
7
The D[0–31] and DP[0–3] input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input
signal is asserted.
Table 6. Bus Operation Timing
1
(continued)
Num
Characteristic
50 MHz
66 MHz
80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min
Max
Min
Max
Min
Max
D =FFACTOR x 1000
F
(D
50
- 20 x FFACTOR)
+
D =FFACTF
(D
50
-20 x FFACTOR)
+
+1ns(CAP LOAD - 50) / 10
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