參數(shù)資料
型號(hào): XPC850SRZT80B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Communications Controller Hardware Specifications
中文描述: 32-BIT, 80 MHz, RISC PROCESSOR, PBGA256
封裝: PLASTIC, BGA-256
文件頁(yè)數(shù): 18/68頁(yè)
文件大?。?/td> 384K
代理商: XPC850SRZT80B
18
MPC850 (Rev. A/B/C) Hardware Specifications
MOTOROLA
Layout Practices
Figure 2 is the control timing diagram.
Figure 2. Control Timing
8
The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects controlled by the UPM in the memory controller, for data beats where DLT3
= 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.
The timing B30 refers to CS when ACS = '00' and to WE[0:3] when CSNT = '0'.
10
The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in
B37 and B38 are specified to enable the freeze of the UPM output signals.
11
The AS signal is considered asynchronous to CLKOUT.
9
CLKOUT
Outputs
A
B
2.0 V
0.8 V
0.8 V
2.0 V
2.0 V
0.8 V
2.0 V
0.8 V
Outputs
2.0 V
0.8 V
2.0 V
0.8 V
B
A
Inputs
2.0 V
0.8 V
2.0 V
0.8 V
D
C
Inputs
2.0 V
0.8 V
2.0 V
0.8 V
C
D
A
Maximum output delay specification
B
Minimum output hold time
C
Minimum input setup time specification
D
Minimum input hold time specification
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XPC850ZT50B 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Communications Controller Hardware Specifications