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R
XCR3320: 320 Macrocell SRAM CPLD
DS033 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
18
This product has been discontinued. Please see
for details.In applications in which a serial EEPROM stores multiple
configuration programs, the subsequent configuration pro-
gram(s) are stored in EEPROM locations that follow the
last address for the previous configuration program. The
user must ensure that the serial EEPROMs address pointer
is not reset, causing the first device configuration to be
reloaded.
Contention on the XCR3320
’
s din pin must be avoided.
During configuration, din receives configuration data. After
configuration, it is a user I/O.
Master Parallel Mode
The master parallel configuration mode is generally used to
interface to industry-standard byte-wide memory such as
256K and larger EEPROMs.
Figure 19
provides the inter-
face for master parallel mode. The XCR3320 outputs a
20-bit address on A[19:0] to memory and reads one byte of
configuration data every eighth cclk. The parallel bytes are
internally serialized starting with the least significant bit,
D0. The starting memory address is 00000 Hex and the
XCR3320 increments the address for each byte loaded.
The starting address is output when the device enters the
configuration state. The XCR3320 latches the data byte on
the second rising edge of cclk. This next data byte is
latched in the XCR3320 seven cclk cycles later.
SP00676
DESIGN COMPILATION AND FIT
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jed
PROM PROGRAMMER
SLAVE SERIAL CONFIGURA ION
Figure 19: Master
t
H
SP00585
t
D
BYTE N
BYTE N + 1
D0
D1
D2
D3
D4
D5
D6
D7
t
S
A[19:0]
D[7:0]
CCLK
DOUT
D0
D1
D2
D3
BYTE N
BYTE N + 1
t
CH
t
CL
Figure 20: Master Parallel Configuration Mode Timing Diagram