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XCR3320: 320 Macrocell SRAM CPLD
DS033 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
10
This product has been discontinued. Please see
for details.XCR3320 States Of Operation
Prior to becoming operational, the XCR3320 goes through
a sequence of states, including initialization, configuration,
and start-up. This section discusses these three states. In
the master configuration modes, the XCR3320 is the
source of configuration clock (cclk).
When configuration is initiated, a counter in the XCR3320
is set to zero and begins to count configuration clock cycles
applied to the XCR3320. As each configuration data frame
is supplied to the XCR3320, it is internally assembled into
data words. Each data word is loaded into the internal con-
figuration memory. The configuration loading process is
complete when the internal length count equals the loaded
length count in the length count field, and the required end
of configuration frame is written.
All configuration I/Os used as inputs operate with TTL-level
input thresholds during configuration. All I/Os that are not
used during the configuration process are 3-stated with
internal pull-downs. During configuration, registers are
reset. The combinatorial logic begins to function as the
XCR3320 is configured.
Figure 6
shows the flow between
the initialization, configuration, and start-up states.
Figure 9
gives the general timing information for configuring the
device.
Figure 8: Chart Of Initialization, Configuration, and Operating States
START-UP
– ALL MACROCELL FF’S ARE RESET
SP00622
POWER-UP
– POWER-ON TIME DELAY
– crcerrn HIGH
INITIALIZATION
– hdc LOW, ldcn HIGH
– done LOW
resetn
OR
LOW
CONFIGURATION
– M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME WRITTEN
– hdc HIGH, ldcn LOW
– dout ACTIVE
– crcerrn HIGH, done LOW
rOR
prgmn
LOW
prgmn
LOW
OPERATION
– I/O BECOMES ACTIVE
NO
YES
crcerrn LOW
ECRC
DEVICE CONFIGURATION COMPLETE
– done RELEASED
– dout ACTIVE
done
HIGH
NO
YES