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| 型號： | XCR3320-8TQ144I |
| 文件頁數(shù)： | 24/43頁 |
| 文件大?。?/td> | 396K |
| 代理商： | XCR3320-8TQ144I |
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Daisy Chain Operation
Multiple XCR3320s can be configured by using a
daisy-chain of XCR3320s. Daisy-chaining uses a lead
XCR3320 and one or more XCR3320s configured in slave
serial mode. The lead XCR3320 can be configured in any
mode.
Figure 27
shows the connections for loading multiple
XCR3320s in a daisy-chain configuration with the lead
devices configured in master parallel mode.
Figure 28
shows the connections for loading multiple XCR3320
’
s with
the lead device configured in master serial mode.
Daisy-chained XCR3320s are connected in series. An
upstream XCR3320 which has received the preamble out-
puts a high on dout, ensuring that downstream XCR3320s
do not receive frame start bits. When the lead device
receives the postamble, its configuration is complete. At
this point, the configuration RAM of the lead device is full
and its done pin is released. The lead device continues to
load configuration data until the internal frame bit counter
reaches the length count or all the done pins of the chain
have gone high. Since the configuration RAM of the lead
device is full, this data is shifted out serially to the down-
stream devices on the dout pin. As the configuration is
completed for the downstream devices, each will release its
done pin. Because the done pins of each device in the
chain are wire-anded together, the done pin will be pulled
high when all devices in the daisy-chain have completed
configuration. All devices now move to the start-up state
simultaneously.
The generation of cclk for the daisy-chained devices which
are in slave serial mode differs depending on the configura-
tion mode of the lead device. A master parallel mode device
uses its internal timing generator to produce an internal
cclk. If the lead device is configured in either synchronous
peripheral, slave serial mode, or slave parallel mode, cclk is
an input and is mated to the lead device and to all of the
daisy-chained devices in parallel. The configuration data is
read into din of slave devices on the positive edge of cclk,
and shifted out dout on the negative edge of cclk. Note that
daisy-chain operation is limited to a cclk frequency of
1 MHz. If a CRC error or an invalid preamble is detected by
a slave device, crcerrn will be pulled low and in turn pull
prgmn low, halting configuration for all devices. If a CRC
error is detected by the master device, hdc will be pulled
low, resetting the EEPROM to the first address and restart-
ing configuration.
The development software can create a composite configu-
ration file for configuring daisy-chained XCR3320s. The
configuration data consists of multiple concatenated data
packets.
OE
CE
SP00670
EEPROM
D[7:0]
A[19:0]
cclk
A[19:0]
D[7:0]
done
prgmn
M2
M1
M0
cclk
din
MASTER
PARALLEL/LEAD
SLAVE #2
done
prgmn
M2
M1
M0
crcerrn
dout
hdc
ldcn
crcerrn
hdc
ldcn
dout
PROGRAM
V
CC
cclk
din
SLAVE #1
done
prgmn
M2
M1
M0
crcerrn
dout
hdc
ldcn
V
CC
V
CC
V
CC
V
CC
M3
M3
M3
Figure 27: Daisy-Chain Schematic with Lead Device in Master Parallel
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