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參數(shù)資料
| 型號： | XCF16PVOG48C |
| 廠商： | XILINX INC |
| 元件分類： | DRAM |
| 英文描述： | Platform Flash In-System Programmable Configuration PROMS |
| 中文描述： | 16M X 1 CONFIGURATION MEMORY, PDSO48 |
| 封裝： | LEAD-FREE, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 21/46頁 |
| 文件大?。?/td> | 525K |
| 代理商： | XCF16PVOG48C |
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
21
R
Figure 13:
Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode
Notes:
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2. For compatible voltages, refer to the appropriate data sheet.
3. RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4. The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5. In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or optionally the
CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal is
used, then it must be tied to a 4.7K
Ω
resistor pulled up to V
CCO
.
6 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be
tied to V
CCO
via a 4.7 k
Ω
pull-up resistor
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
VCCINT
V
CCO(2)
V
CCJ(2)
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
D[0:7]
CLK
(5)
CE
CEO
OE/RESET
CF
(6)
BUSY
(4)
TDO
Xilinx FPGA
Slave SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
(4)
TDI
TMS
TCK
MODE PINS
(1)
RDWR_B
CS_B
TDO
V
CCJ
V
CCO
V
CCINT
4
Ω
4
Ω
(1)
V
CCO(2)
TDI
TMS
TCK
TDO
Xilinx FPGA
Slave SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
(4)
TDI
TMS
TCK
MODE PINS
(1)
RDWR_B
CS_B
TDO
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
V
CCINT
V
CCO(2)
V
CCJ(2)
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
D[0:7]
CLK
(5)
CE
CEO
OE/RESET
CF
(6)
BUSY
(4)
TDO
V
CCJ
V
CCO
V
CCINT
1
Ω
I/O
(3)
1
Ω
I/O
(3)
EN_EXT_SEL
REV_SEL[1:0]
CF
DONE
PROG_B
CS_B[1:0]
Design
Revision
Control
Logic
GND
GND
ds123_18_122105
External
(5)
Oscillator
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