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參數(shù)資料
| 型號(hào)： | XCF16PFSG48C |
| 廠商： | XILINX INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | Platform Flash In-System Programmable Configuration PROMS |
| 中文描述： | 16M X 1 CONFIGURATION MEMORY, PBGA48 |
| 封裝： | LEAD-FREE, PLASTIC, TFBGA-48 |
| 文件頁(yè)數(shù)： | 46/46頁(yè) |
| 文件大小： | 525K |
| 代理商： | XCF16PFSG48C |
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
46
R
12/29/05
2.8
Update to the first paragraph of
"IEEE 1149.1 Boundary-Scan (JTAG)," page 5
.
Added JTAG cautionary note to
Page 5
.
Corrected logic values for Erase/Program (ER/PROG) Status field, IR[4], listed under
"XCFxxP
Instruction Register (16 bits wide)," page 6
.
Sections
"XCFxxS and XCFxxP PROM as Configuration Slave with CLK Input Pin as Clock
Source," page 27
,
"XCFxxP PROM as Configuration Master with CLK Input Pin as Clock
Source," page 30
and
"XCFxxP PROM as Configuration Master with Internal Oscillator as Clock
Source," page 33
added to
"AC Characteristics Over Operating Conditions," page 27
.
Notes for
Figure 6, page 14
,
Figure 7, page 15
,
Figure 8, page 16
,
Figure 9, page 17
,
Figure 10,
page 18
,
Figure 11, page 19
,
Figure 12, page 20
, and
Figure 13, page 21
updated to specify the
need for a pull-up resistor if CF is not connected to PROGB.
Enhanced description under section
"CLKOUT," page 8
.
Enhanced description on design revision sampling under section
"Design Revisioning," page 9
.
Figure 4 and Figure 5 renamed to
Table 7, page 6
and
Table 8, page 6
respectively. All tables,
figures, and table and figure references renumber this point forward.
Value for
"ICCINT," page 26
updated from 5mA to 1mA for XCFxxP.
Block diagram in
Figure 2, page 2
updated to show clock source muxing and route clocking to all
functional blocks.
05/09/06
2.9
Added Virtex-5 LX support to
Table 2, page 3
.
"VIL"
maximum for 2.5V operation in
"Recommended Operating Conditions," page 25
updated
to match LVCMOS25 standard.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XCF16PFSG48C4039 | 制造商:Xilinx 功能描述: |
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