參數(shù)資料
型號(hào)： XCF16PFSG48C
廠商： XILINX INC
元件分類： DRAM
英文描述： Platform Flash In-System Programmable Configuration PROMS
中文描述： 16M X 1 CONFIGURATION MEMORY, PBGA48
封裝： LEAD-FREE, PLASTIC, TFBGA-48
文件頁(yè)數(shù)： 36/46頁(yè)
文件大小： 525K
代理商： XCF16PFSG48C
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
36
R
AC Characteristics Over Operating Conditions When Cascading
Symbol
Description
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
Units
Min
Max
Min
Max
T
CDF
CLK to output float delay
(2,3)
when V
CCO
= 2.5V or 3.3V
CLK to output float delay
(2,3)
when V
CCO
= 1.8V
CLK to CEO delay
(3,5)
when V
CCO
= 2.5V or 3.3V
CLK to CEO delay
(3,5)
when V
CCO
= 1.8V
CE to CEO delay
(3,6)
when V
CCO
= 2.5V or 3.3V
CE to CEO delay
(3,6)
when V
CCO
= 1.8V
OE/RESET to CEO delay
(3)
when V
CCO
= 2.5V or 3.3V
OE/RESET to CEO delay
(3)
when V
CCO
= 1.8V
CLKOUT to CEO delay when V
CCO
= 2.5V or 3.3V
CLKOUT to CEO delay when V
CCO
= 1.8V
CLKOUT to output float delay
when V
CCO
= 2.5V or 3.3V
CLKOUT to output float delay when V
CCO
= 1.8V
–
25
–
20
ns
–
35
–
20
ns
T
OCK
–
20
–
20
ns
–
35
–
20
ns
T
OCE
–
20
–
80
ns
–
35
–
80
ns
T
OOE
–
20
–
80
ns
–
35
–
80
ns
T
COCE
–
–
–
20
ns
–
–
–
20
ns
T
CODF
–
–
–
25
ns
–
–
–
25
ns
Notes:
1.
2.
3.
4.
5.
AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
Guaranteed by design, not tested.
All AC parameters are measured with V
IL
= 0.0V and V
IH
= 3.0V.
For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins are set to persist as configuration pins, the minimum
period is increased based on the CLK to CEO and CE to data propagation delays:
- T
CYC
minimum = T
OCK
+ T
CE
+ FPGA Data setup time.
- T
CAC
maximum = T
OCK
+ T
CE
For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins become general I/O pins after configuration; to allow for
the disable to propagate to the cascaded PROMs and to avoid contention on the data lines following configuration, the minimum
period is increased based on the CE to CEO and CE to data propagation delays:
- T
CYC
minimum = T
OCE
+ T
CE
- T
CAC
maximum = T
OCK
+ T
CE
6.
OE/RESET
CE
CLK
CLKOUT
(optional)
DATA
CEO
T
OCE
T
OOE
First Bit
Last Bit
T
CDF
T
CODF
T
OCK
T
COCE
ds123_23_102203
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