參數(shù)資料
型號(hào): XC850DECZT50BUR2
廠商: Freescale Semiconductor
文件頁數(shù): 51/72頁
文件大小: 0K
描述: IC MPU POWERQUICC 50MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 500
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 帶卷 (TR)
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
55
CPM Electrical Characteristics
Figure 53. Ethernet Collision Timing Diagram
Figure 54. Ethernet Receive Timing Diagram
134
TENA inactive delay (from TCLKx rising edge)
10.00
50.00
ns
138
CLKOUT low to SDACK asserted 2
20.00
ns
139
CLKOUT low to SDACK negated 2
20.00
ns
1
The ratios SyncCLK/RCLKx and SyncCLK/TCLKx must be greater or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory.
Table 20. Ethernet Timing (continued)
Num
Characteristic
All Frequencies
Unit
Min
Max
CLSN(CTSx)
120
(Input)
RCLKx
121
RXDx
(Input)
121
RENA(CDx)
(Input)
125
124
123
127
126
Last Bit
122
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