參數(shù)資料
型號(hào): XC850DECZT50BUR2
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 50/72頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 50MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 500
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 帶卷 (TR)
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
54
Freescale Semiconductor
CPM Electrical Characteristics
Figure 52. HDLC Bus Timing Diagram
8.7
Ethernet Electrical Specifications
Table 20 provides the Ethernet timings as shown in Figure 53 to Figure 55.
Table 20. Ethernet Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
120
CLSN width high
40.00
ns
121
RCLKx rise/fall time (x = 2, 3 for all specs in this table)
15.00
ns
122
RCLKx width low
40.00
ns
123
RCLKx clock period 1
80.00
120.00
ns
124
RXDx setup time
20.00
ns
125
RXDx hold time
5.00
ns
126
RENA active delay (from RCLKx rising edge of the last data bit)
10.00
ns
127
RENA width low
100.00
ns
128
TCLKx rise/fall time
15.00
ns
129
TCLKx width low
40.00
ns
130
TCLKx clock period1
99.00
101.00
ns
131
TXDx active delay (from TCLKx rising edge)
10.00
50.00
ns
132
TXDx inactive delay (from TCLKx rising edge)
10.00
50.00
ns
133
TENA active delay (from TCLKx rising edge)
10.00
50.00
ns
TCLKx
CTSx
(Echo Input)
102
100
104
TXDx
(Output)
102
101
RTSx
(Output)
103
104
107
105
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