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參數(shù)資料
| 型號： | XC850DECZT50BUR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 34/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC 50MHZ 256-PBGA |
| 標準包裝： | 500 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 50MHz |
| 電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應商設(shè)備封裝： | 256-PBGA（23x23） |
| 包裝： | 帶卷 (TR) |
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MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
4
Freescale Semiconductor
Features
— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture)
– Caches are two-way, set-associative
– Physically addressed
– Cache blocks can be updated with a 4-word line burst
– Least-recently used (LRU) replacement algorithm
– Lockable one-line granularity
— Memory management units (MMUs) with 8-entry translation lookaside buffers (TLBs) and
fully-associative instruction and data TLBs
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
8 Mbytes; 16 virtual address spaces and eight protection groups
Advanced on-chip emulation debug mode
Data bus dynamic bus sizing for 8, 16, and 32-bit buses
— Supports traditional 68000 big-endian, traditional x86 little-endian and modified little-endian
memory systems
— Twenty-six external address lines
Completely static design (0–80 MHz operation)
System integration unit (SIU)
— Hardware bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Memory controller (eight banks)
— Glueless interface to DRAM single in-line memory modules (SIMMs), synchronous DRAM
(SDRAM), static random-access memory (SRAM), electrically programmable read-only
memory (EPROM), flash EPROM, etc.
— Memory controller programmable to support most size and speed memory interfaces
— Boot chip-select available at reset (options for 8, 16, or 32-bit memory)
— Variable block sizes, 32 Kbytes to 256 Mbytes
— Selectable write protection
— On-chip bus arbiter supports one external bus master
— Special features for burst mode support
General-purpose timers
— Four 16-bit timers or two 32-bit timers
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC-850DSR | 功能描述:LAN/電信/電纜測試 LAN OTDR 850nm Duplex; Reflective D RoHS:否 制造商:Megger 設(shè)備類型:General Purpose Time Domain Reflectometer 電纜類型: |
| XC-850DST | 功能描述:LAN/電信/電纜測試 LAN OTDR 850nm Duplex; Transmissive RoHS:否 制造商:Megger 設(shè)備類型:General Purpose Time Domain Reflectometer 電纜類型: |
| XC-850SSR | 功能描述:LAN/電信/電纜測試 LAN OTDR 850nm Simplex: Reflective RoHS:否 制造商:Megger 設(shè)備類型:General Purpose Time Domain Reflectometer 電纜類型: |
| XC-850SST | 功能描述:LAN/電信/電纜測試 LAN OTDR 850nm Simplex: Transmissiv RoHS:否 制造商:Megger 設(shè)備類型:General Purpose Time Domain Reflectometer 電纜類型: |
| XC-8513DSR | 功能描述:LAN/電信/電纜測試 LAN OTDR RoHS:否 制造商:Megger 設(shè)備類型:General Purpose Time Domain Reflectometer 電纜類型: |
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