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參數(shù)資料
| 型號： | XC3190L-3TQ176C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 320 CLBS, 5000 GATES, 270 MHz, PQFP176 |
| 封裝： | PLASTIC, TQFP-176 |
| 文件頁數(shù)： | 59/76頁 |
| 文件大?。?/td> | 731K |
| 代理商： | XC3190L-3TQ176C |
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R
November 9, 1998 (Version 3.1)
7-61
XC3000 Series Field Programmable Gate Arrays
7
XC3100L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
1. The CLB K to Q delay (T
CKO
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data
In hold time requirement (T
CKDI
, #5) of any CLB on the same die.
2. T
ILO
, T
QLO
and T
ICK
are specified for 4-input functions. For 5-input functions or base FGM functions, each of these
specifications for the XC3100L family increase by 0.35 ns (-3) and 0.29 ns (-2).
Speed Grade
Symbol
-3
-2
Description
Min
Max
Min
Max
Units
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
Set-up time before clock K
Logic Variables
Data In
Enable Clock
Reset Direct Inactive
Hold Time after clock K
Logic Variables
Data In
Enable Clock
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset (RESET Pad)
RESET width (Low)
1
T
ILO
2.7
2.2
ns
8
T
CKO
T
QLO
2.1
4.3
1.7
3.5
ns
ns
A, B, C, D, E
DI
EC
RD
2
4
6
T
ICK
T
DICK
T
ECCK
2.1
1.4
2.7
1.0
1.8
1.3
2.5
1.0
ns
ns
ns
ns
A, B, C, D, E
DI
EC
3
5
7
T
CKI
T
CKDI
T
CKEC
0
0.9
0.7
0
0.9
0.7
ns
ns
ns
11
12
T
CH
T
CL
F
CLK
1.6
1.6
270
1.3
1.3
325
ns
ns
MHz
13
9
T
RPW
T
RIO
2.7
3.1
2.3
2.7
ns
ns
(XC3142L)
delay from RESET pad to outputs X or Y
T
MRW
T
MRQ
12.0
12.0
12.0
12.0
ns
ns
Advance
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