參數(shù)資料
型號(hào)： XC3190L-3TQ176C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 320 CLBS, 5000 GATES, 270 MHz, PQFP176
封裝： PLASTIC, TQFP-176
文件頁(yè)數(shù)： 41/76頁(yè)
文件大?。?/td> 731K
代理商： XC3190L-3TQ176C
R
November 9, 1998 (Version 3.1)
7-43
XC3000 Series Field Programmable Gate Arrays
7
XC3000A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
1. Timing is based on the XC3042A, for other devices see timing calculator.
2. The CLB K to Q output delay (T
CKO
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (T
CKDI
, #5) of any CLB on the same die.
Speed Grade
Symbol
-7
-6
Description
Min
Max
Min
Max
Units
Combinatorial Delay
Logic Variables
A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode
1
T
ILO
5.1
5.6
4.1
4.6
ns
ns
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
Set-up time before clock K
Logic Variables
A, B, C, D, E
FG Mode
F and FGM Mode
Data In
DI
Enable Clock
EC
Hold Time after clock K
Logic Variables
A, B, C, D, E
Data In
DI
2
Enable Clock
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset (RESET Pad)
1
RESET width (Low)
delay from RESET pad to outputs X or Y
8
T
CKO
T
QLO
4.5
9.5
10.0
4.0
8.0
8.5
ns
ns
ns
2
4
6
T
ICK
T
DICK
T
ECCK
4.5
5.0
4.0
4.5
3.5
4.0
3.0
4.0
ns
ns
ns
ns
3
5
7
T
CKI
T
CKDI
T
CKEC
0
1.0
2.0
0
1.0
2.0
ns
ns
ns
11
12
T
CH
T
CL
F
CLK
4.0
4.0
113.0
3.5
3.5
135.0
ns
ns
MHz
13
9
T
RPW
T
RIO
6.0
6.0
5.0
5.0
ns
ns
T
MRW
T
MRQ
16.0
19.0
14.0
17.0
ns
ns
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