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參數(shù)資料
| 型號： | XC3043L |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 40/76頁 |
| 文件大?。?/td> | 731K |
| 代理商： | XC3043L |
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R
XC3000 Series Field Programmable Gate Arrays
7-42
November 9, 1998 (Version 3.1)
XC3000A Absolute Maximum Ratings
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.
XC3000A Global Buffer Switching Characteristics Guidelines
Note:
1. Timing is based on the XC3042A, for other devices see timing calculator.
Symbol
V
CC
V
IN
V
TS
T
STG
T
SOL
Description
Units
V
V
V
°
C
°
C
°
C
°
C
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in.)
Junction temperature plastic
Junction temperature ceramic
–0.5 to +7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–65 to +150
+260
+125
+150
T
J
Speed Grade
Symbol
-7
-6
Description
Max
Max
Units
Global and Alternate Clock Distribution
1
Either:
Normal
IOB input pad through clock buffer
to any CLB or IOB clock input
Or:
Fast
(CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TBUF
driving a Horizontal Longline (L.L.)
1
I to L.L. while T is Low (buffer active)
T
↓
to L.L. active and valid with single pull-up resistor
T
↓
to L.L. active and valid with pair of pull-up resistors
T
↑
to L.L. High with single pull-up resistor
T
↑
to L.L. High with pair of pull-up resistors
BIDI
Bidirectional buffer delay
T
PID
T
PIDC
7.5
6.0
7.0
5.7
ns
ns
T
IO
T
ON
T
ON
T
PUS
T
PUF
4.5
9.0
11.0
16.0
10.0
4.0
8.0
10.0
14.0
8.0
ns
ns
ns
ns
ns
T
BIDI
1.7
1.5
ns
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