參數(shù)資料
型號(hào)： XA-SCC
廠商： NXP Semiconductors N.V.
英文描述： CMOS 16-bit communications microcontroller
中文描述： 的CMOS 16位微控制器的通信
文件頁(yè)數(shù)： 35/42頁(yè)
文件大?。?/td> 229K
代理商： XA-SCC
Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
35
A
WE
D
SU01136
CLKOUT
RAS (CS)
CAS (BHE/BLE)
NOTE:
If only one byte is being written, then only the corresponding CAS signal goes active. On 8 bit bus, CASH is inactive, and CASL goes active for
both even and odd addressed bytes.
: OE is inactive during all writes.
t
CHDV
VALID DATA
t
CHSH
NOTE 1
t
CHSH
t
CHAH
t
CHSL
t
CHAH
t
CHAV
RAS ADDRESS
CAS ADDRESS
t
CHSL
t
AVSL
t
AVSL
Figure 15. DRAM Write (on 16 Bit Bus, also 8 Bit Write on 8 Bit Bus)
ééééé
On all cycles on 8 bit bus, BHE remains high (inactive).
DRIVEN BY XA
A0
CS
BLE
OE
NOTE 2
SU01137
CLKOUT
A19–A1
D7–D0
NOTE 3
t
CHSL
t
CHAV
t
CHSH
t
OHDE
NOTE 2
t
DIH
DRIVEN
BY XA
EVEN BYTE ADDRESS
ODD BYTE ADDRESS
t
CHAV
WARNING:
On the external bus, ALL XA–SCC reads are 16 bit Reads. If the CPU instruction only specifies 8 bits, then the CPU uses the appropriate byte, and discards the extra
byte. Thus “8 Bit Reads” and “16 bit Reads” appear to be identical on the bus. On an 8 bit bus, this will appear as two consecutive 8 bit reads even though the CPU will only use one
of the two bytes.
WARNING:
Some 8 bit I/O devices (especially FIFOs) cannot operate correctly with 2 bytes being Read for a 1 Byte Read. The most common (and least expensive) solution is to
operate these 8 bit devices on a 16 bit bus, and access them in software on all odd byte (or all even byte) boundaries. An added benefit of this technique is that byte reads are faster
than on an 8 bit bus, because only 1 word is fetched (a single read) instead of 2 consecutive bytes.
t
AVSL
t
DIS
t
DIS
t
AHDR
Figure 16. Generic (SRAM, Flash, I/O Device, etc.) Read (16 Bit or 8 Bit) on 8 Bit Bus
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