參數(shù)資料
型號(hào)： XA-SCC
廠商： NXP Semiconductors N.V.
英文描述： CMOS 16-bit communications microcontroller
中文描述： 的CMOS 16位微控制器的通信
文件頁數(shù)： 29/42頁
文件大小： 229K
代理商： XA-SCC
Philips Semiconductors
Preliminary specification
XA-SCC
CMOS 16-bit communications microcontroller
1999 Mar 29
29
PRELIMINARY AC ELECTRICAL CHARACTERISTICS (5.0V
V
DD
= 5.0V
10%, T
amb
= –40 C to +85 C (industrial)
10%)
1
LIMITS
SYMBOL
All Cycles
F
C
FIGURE
PARAMETER
MIN
MAX
UNIT
System Clock Frequency
0
30
MHz
t
C
25
System Clock Period = 1/F
C
XTALIN High Time
33.33
–
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
t
AVSL
t
CHAH
t
CHAV
t
CHSH
t
CHSL
t
CODH
25
t
C
* 0.5
t
C
* 0.4
–
–
ns
25
XTALIN Low Time
–
ns
25
XTALIN Rise Time
5
ns
25
XTALIN Fall Time
–
5
ns
All
Address Valid to Strobe low
Address hold after CLKOUT rising edge
9
t
C
– 21
1
–
ns
All
–
ns
All
Delay from CLKOUT rising edge to address valid
Delay from CLKOUT rising edge to Strobe High
9
–
1
1
25
ns
All
21
ns
All
Delay from CLKOUT rising edge to Strobe Low
9
19
ns
26
ClkOut Duty Cycle High (into 40pF max.)
(See
Warning
Note 5 on page 31.)
t
CHCX
–7
t
CHCX
+3
ns
t
CPWH
13, 14, 16,
20, 21, 22
CAS Pulse Width High
t
C
– 12
–
ns
t
CPWL
13, 21
CAS Pulse Width Low
t
C
– 10
–
ns
All DRAM cycles
t
RP
24
RAS precharge time, thus minimum RAS high time
8
(n * t
C
) –16
note 8
–
ns
Generic Data Read Only
t
AHDR
9, 16
Address hold (A19–A1 only, not A0) after CS, BLE, BHE rise at end
of Generic Data Read Cycle (not code fetch)
t
C
–12
–
ns
Data Read and Instruction Fetch Cycles
t
DIS
9, 10,
12–14, 16,
17, 20, 21
Data In Valid setup to ClkOut rising edge
25
–
ns
t
DIH
t
OHDE
Data In Valid hold after ClkOut rising edge
2
0
–
ns
10, 12, 13,
16, 20, 21
OE high to XA Data Bus Driver Enable
t
C
– 14
–
ns
Write Cycles
t
CHDV
t
DVSL
t
SHAH
t
SHDH
Refresh
t
CLRL
Wait Input
t
WS
t
WH
NOTE:
1. See notes after the 3.3V AC timing table.
Clock High to Data Valid
–
25
ns
Data Valid prior to Strobe Low
t
C
– 23
t
C
– 25
t
C
– 25
–
ns
11, 16
Minimum Address Hold Time after strobe goes inactive
–
ns
Data hold after strobes (CS and BHE/BLE) high
–
ns
21
CAS low to RAS low
t
C
– 15
–
ns
24
WAIT setup (stable high or low) to CLKOUT rising edge
20
–
ns
24
WAIT hold (stable high or low) after CLKOUT rising edge
0
–
ns
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