參數(shù)資料
型號(hào)： X88C75LM
英文描述： Port Expander and E2 Memory
中文描述： 端口擴(kuò)展和E2內(nèi)存
文件頁(yè)數(shù)： 3/27頁(yè)
文件大?。?/td> 125K
代理商： X88C75LM
X88C75 SLIC
E
2
3
an authorized service center). The Block Protect con-
figuration is stored in a nonvolatile register, ensuring
that the configuration data will be maintained after the
device is powered-down.
The X88C75 write control input, serves as an external
control over the completion of a previously initiated page
load cycle.
The X88C75 also features the industry standard 5V E
2
memory characteristics such as byte or page mode write
and Toggle Bit Polling.
Read
A HIGH to LOW transition on ALE latches the address;
the data will be output on the AD pins after either
RD
or
PSEN
goes LOW (t
RDLV
).
Write
A write is performed by latching the addresses on the
falling edge of ALE. The
WR
is strobed LOW followed by
valid data being presented on the AD
0
–AD
7
pins. The
data will be latched into the X88C75 on the rising edge
of
WR
.
Page Write Operation
The X88C75 supports page mode write operations. This
allows the microcontroller to write from one to thirty-two
bytes of data to the X88C75. Each individual write within
a page write operation must conform to the byte write
timing requirements. The falling edge of
WR
starts a
timer delaying the internal programming cycle 100
μ
s:
therefore, each successive write operation must begin
within 100
μ
s of the last byte written. The waveform
on page 4 illustrates the sequence and timing
requirements.
PIN DESCRIPTIONS
PIN NAME
I/O
DESCRIPTION
RESET
I
RESET is used to initialize the internal static registers and has no effect on the E
2
memory opera-
tions. The default active level is HIGH, but it can be reconfigured in EEM register.
Content of E
2
memory can be read by lowering the
PSEN
and holding both
RD
and
WR
HIGH. The
device then places on the data bus (AD
7
–AD
0
) the contents of E
2
memory at the latched address.
The STRA controls port A and STRB controls port B. When ports are configured as inputs, a valid
transition on their strobe pins will latch into their port data register the data present at the port input
pins. Writing to an output port data register generates a pulse of fixed duration on its corresponding
strobe pin. The output data presented at the output pins stay valid until the next data is written to the
output port data register.
The I/O lines of port A. The output driver can be configured as either CMOS or open-drain using the
AWO bit in CR. The I/O direction bit (DIRA) in CR is used to select port A I/O mode.
The I/O lines of port B. The output driver can be configured as either CMOS or open-drain using the
BWO bit in CR. The I/O direction bit (DIRB) in CR is used to select port B I/O mode.
Non-multiplexed high-order Address Bus inputs for the upper byte of the address.
Multiplexed low-order Address and Data Bus. The addresses are latched when ALE makes a HIGH
to LOW transition.
During a byte/page write cycle
WR
is brought LOW while
RD
is held HIGH and the data is placed on
the Data Bus. The rising edge of
WR
will latch the data into the device.
The
RD
input is active LOW and is used to read content of either the E
2
memory or the SFR at the
latched address. Both
PSEN
and
WR
signals must be held HIGH during
RD
controlled read
operation.
The
IRQ
is an open-drain output. It can be configured to signal latching of new data into any of the
ports, and/or completion of the E
2
memory internal write cycle.
WC
input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to
disable write to the E
2
memory. Taking
WC
HIGH prior to t
BLC
(100
μ
s, the time delay from the last
write cycle to the start of internal programming cycle) will inhibit the write operation.
The device select (
CE
) is an active LOW input. This signal has to be asserted prior to ALE HIGH to
LOW transition in order to generate a valid internal device select signal. Holding this pin HIGH and
ALE LOW will place the device in standby mode. The ports stay active at all times.
Address Latch Enable input is used to latch the addresses present on the address lines A
15
–A
8
and
AD
7
–AD
0
into the device. The addresses are latched when ALE transitions from HIGH to LOW.
PSEN
I
STRA, STRB
I/O
PA
7
–PA
0
I/O
PB
7
–PB
0
I/O
A
15
–A
8
AD
7
–AD
0
I
I/O
WR
I
RD
I
IRQ
O
WC
I
CE
I
ALE
I
2887 PGM T01.1
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