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參數(shù)資料
| 型號： | WEDPND16M72S-250BM |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.8 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 441K |
| 代理商： | WEDPND16M72S-250BM |
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPND16M72S-XBX
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is is-
sued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in
the current bank and does not violate any other timing pa-
rameters. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise
BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank.
A PRECHARGE command will be treated as a NOP if there is
no open row in that bank (idle state), or if the previously
open row is already in the process of precharging.
AUTO PRECHARGE is a feature which performs the same indi-
vidual-bank PRECHARGE function described above, but without
requiring an explicit command. This is accomplished by using
A10 to enable AUTO PRECHARGE in conjunction with a specific
READ or WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE burst. AUTO
PRECHARGE is nonpersistent in that it is either enabled or dis-
abled for each individual READ or WRITE command. The device
supports concurrent auto precharge if the command to the other
bank does not interrupt the data transfer to the current bank.
AUTO PRECHARGE ensures that the precharge is initiated at the
earliest valid stage within a burst. This “earliest valid stage” is
determined as if an explicit precharge command was is-
sued at the earliest possible time, without violating tRAS
(MIN).The user must not issue another command to the same
bank until the precharge time (tRP) is completed. This is deter-
mined as if an explicit PRECHARGE command was issued at
the earliest possible time, without violating tRAS (MIN).
The BURST TERMINATE command is used to truncate READ
bursts (with auto precharge disabled). The most recently
registered READ command prior to the BURST TERMINATE
command will be truncated. The open page which the READ
burst was terminated from remains open.
PRECHARGE
AUTO PRECHARGE
AUTO REFRESH is used during normal operation of the DDR
SDRAM and is analogous to CAS-BEFORE-RAS (CBR) RE-
FRESH in conventional DRAMs. This command is nonpersis-
tent, so it must be issued each time a refresh is required.
The addressing is generated by the internal refresh control-
ler. This makes the address bits “Don’t Care” during an AUTO
REFRESH command. Each DDR SDRAM requires AUTO RE-
FRESH cycles at an average interval of 7.8125
ms (maximum).
To allow for improved efficiency in scheduling and switch-
ing between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, mean-
ing that the maximum absolute interval between any AUTO
REFRESH command and the next AUTO REFRESH command
is 9 x 7.8125
ms (70.3ms). This maximum absolute interval is
to allow future support for DLL updates internal to the DDR
SDRAM to be restricted to AUTO REFRESH cycles, without
allowing excessive drift in tAC between updates.
Although not a JEDEC requirement, to provide for future func-
tionality features, CKE must be active (High) during the AUTO
REFRESH period. The AUTO REFRESH period begins when the
AUTO REFRESH command is registered and ends tRFC later.
The SELF REFRESH command can be used to retain data in
the DDR SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the DDR SDRAM re-
tains data without external clocking. The SELF REFRESH com-
mand is initiated like an AUTO REFRESH command except
CKE is disabled (LOW). The DLL is automatically disabled
upon entering SELF REFRESH and is automatically enabled
upon exiting SELF REFRESH (200 clock cycles must then
occur before a READ command can be issued). Input sig-
nals except CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable prior to CKE going back
HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP
commands issued for tXSNR, because time is required for the
completion of any internal refresh in progress.
A simple algorithm for meeting both refresh and DLL re-
quirements is to apply NOPs for 200 clock cycles before
applying any other command.
* Self refresh available in commercial and industrial temperatures only.
AUTO REFRESH
SELF REFRESH*
BURST TERMINATE
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