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參數(shù)資料
| 型號(hào)： | WED9LAPC2C16V8BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA192 |
| 封裝： | 21 X 21 MM, BGA-192 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 933K |
| 代理商： | WED9LAPC2C16V8BC |
19
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2C16V8BC
July, 2000
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIG. 12 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP
@ BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Burst Stop
Precharge
(A-Bank)
DON’T CARE
RAa
CAa
CAb
RAa
Note 2
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
QAa0
QAa1
QAa2
QAa3
QAa4
1
2
1
Notes:
1.
At full page mode, burst is end at the end of burst. So auto precharge is possible.
2.
About the valid VCDATAs after burst stop, it is the same as the case of VCRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on
each of them. But at burst write, burst stop and VCRAS# interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle.”
3.
Burst stop is valid at every burst length.
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| WED9LAPC2C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LC6416V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1310BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
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