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參數(shù)資料
| 型號： | WED9LAPC2C16P8BI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, PBGA153 |
| 封裝： | 14 X 22 MM, BGA-153 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 693K |
| 代理商： | WED9LAPC2C16P8BI |
12
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED9LAPC2B16P8BC
November 2001
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
FIGURE 6 – SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
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16
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18
19
GCK
VCRAS#
VCCAS#
VCADDR
VCBS
VCADDR9/AP
VCDATA
VCWE#
VCDQM#
CL = 2
CL = 3
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
tRCD
Note 2
Ra
Ca0
Cb0
Cd0
Cc0
Ra
Note 3
tCDL
Note 1
tRDL
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb2
Qb1
Qb2
Notes:
1. To write data before burst read ends. VCDQM# should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. VCDQM# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data
after Row precharge cycle will be masked internally.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED9LAPC2C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC2C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LAPC3C16V8BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512K x 32 SSRAM / 1M x 64 SDRAM |
| WED9LC6416V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
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