參數(shù)資料
型號: W3E232M16S-266STIG
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁數(shù): 13/22頁
文件大小: 0K
代理商: W3E232M16S-266STIG
W3E232M16S-XSTX
20
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY*
49. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satised.
50. ICC2N species the DQ, DQS, and DQM to be driven to a valid high or low logic
level. ICC2Q is similar to ICC2F except ICC2Q species the address and control inputs
to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.”
51. Whenever the operating frequency is altered, not including jitter, the DLL is
required to be reset followed by 200 clock cycles before any READ command.
52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC coltage range of 2.6V ± 100mV.
53. One TSOP current mode, one TSOP in precharge power down standby mode
(IDD2P).
54. Both TSOPs in same current mode.
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