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參數(shù)資料
| 型號(hào)： | W25X32AVZPIG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類(lèi)： | PROM |
| 英文描述： | 4M X 8 FLASH 2.7V PROM, PDSO8 |
| 封裝： | 6 X 5 MM, GREEN, WSON-8 |
| 文件頁(yè)數(shù)： | 14/45頁(yè) |
| 文件大?。?/td> | 1308K |
| 代理商： | W25X32AVZPIG |
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W25X32A
Publication Release Date: August 7, 2009
- 21 -
Preliminary - Revision B
10.2.9 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins, DO and DIO, instead of just DO. This allows data to be transferred from
the W25X32A at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal
for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-
segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks
is “don’t care”. However, the DIO pin should be high-impedance prior to the falling edge of the first data
out clock.
Figure 10. Fast Read Dual Output Instruction Sequence Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W25X32AVSFIG | 4M X 8 FLASH 2.7V PROM, PDSO16 |
| W26L04AJ-12I | 256K X 16 STANDARD SRAM, 12 ns, PDSO44 |
| W26L04AH-10 | 256K X 16 STANDARD SRAM, 10 ns, PDSO44 |
| W28A | CERPAC, 28 LEAD |
| W2H11A1018AT | 1 FUNCTIONS, 100 V, 0.5 A, FEED THROUGH CAPACITOR |
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| W25X32BVSFIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:32M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI |
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