參數(shù)資料
型號: W25Q80BVSFIG
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 1M X 8 SPI BUS SERIAL EEPROM, PDSO16
封裝: 0.300 INCH, GREEN, PLASTIC, SOIC-16
文件頁數(shù): 28/72頁
文件大?。?/td> 1878K
代理商: W25Q80BVSFIG
W25Q80BV
- 34 -
Byte 1
Byte 2
Byte 3
4
0
4
0
4
0
5
1
5
1
5
1
6
2
6
2
6
2
7
3
7
3
7
3
Byte 1
Byte 2
Byte 3
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
3
Figure 15b. Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10)
Word Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Word Read Quad I/O instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” command prior to E7h. The “Set Burst with Wrap” command can either
enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is
enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte
page. The output data starts at the initial address specified in the instruction, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. See 10.2.18 for detail descriptions.
相關(guān)PDF資料
PDF描述
W25X32AVZPIG 4M X 8 FLASH 2.7V PROM, PDSO8
W25X32AVSFIG 4M X 8 FLASH 2.7V PROM, PDSO16
W26L04AJ-12I 256K X 16 STANDARD SRAM, 12 ns, PDSO44
W26L04AH-10 256K X 16 STANDARD SRAM, 10 ns, PDSO44
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