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參數(shù)資料
| 型號： | W19B320STB9F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | TFBGA-48 |
| 文件頁數(shù)： | 5/52頁 |
| 文件大小： | 1869K |
| 代理商： | W19B320STB9F |
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W19B(L)320ST/B
Publication Release Date: March 23, 2004
- 13 -
Revision A2
The device offers accelerated program operations by the #WP/ACC pin. When the VHH is set at the
#WP/ACC pin, the device automatically enters into the Unlock Bypass mode. Then, the two-cycle
Unlock Bypass program command sequence may be written. To accelerate the operation, the device
must use the higher voltage on the #WP/ACC pin. Please note that the #WP/ACC pin must not be at
VHH in any operation other than accelerated programming; otherwise the device may be damaged. In
addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent
behavior may occur.
6.2.7 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation. Writing two unlock cycles initiates the chip erase command
sequence, which is followed by a set-up command. After chip erase command, two additional unlock
write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system
preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or
timings during these operations is not required in system.
As the Embedded Erase algorithm is complete, the device returns to the read mode and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7,
DQ6, DQ2, or RY/#BY. Please refer to the Write Operation Status section for information on these
status bits.
Any commands written during the chip erase operation will be ignored. However, a hardware reset
shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip
erase command sequence should be reinitiated when the device has returned to reading array data.
6.2.8 Sector Erase Command Sequence
Sector erase is a six-bus cycle operation. Writing two unlock cycles initiates the sector erase
command sequence, which is followed by a set-up command. Two additional unlock cycles are
written, and are then followed by the address of the sector to be erased, and the sector erase
command.
The device does not require the system to preprogram before erase. Before electrical erase, the
Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data
pattern. Any controls or timings during these operations is not required in system.
A sector erase time-out of 50
S occurs after the command sequence is written. Additional sector
addresses and sector erase commands may be written during the time-out period. Loading the sector
erase buffer may be done in any sequence, and the number of sectors may be from one sector to all
sectors. The time between these additional cycles must be less than 50
S; otherwise, erasure may
begin. Any sector erase address and command following the exceeded time-out may or may not be
accepted. To ensure all commands are accepted, processor interrupts be disabled during this time is
recommended. The interrupts can be re-enabled after the last Sector Erase command is written. Any
command other than Sector Erase or Erase Suspend during the time-out period resets the device to
the read mode. The system must rewrite the command sequence and any additional addresses and
commands.
The system can monitor DQ3 to determine whether or not the sector erase timer has timed out (See
the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final #WE
pulse in the command sequence.
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