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VIA Technologies, Inc.
Preliminary
VT83C469
30
Parameter
Description
Min
Max
T1A
A<23:17> Setup to 16-Bit Memory Command
102
T1B
A<23:17> Setup to 8-Bit Memory Command
162
T2
MEMCS16# Valid from A<23:17>
58
T3
MEMCS16# Hold from A<16:00>
31
T4
MEMCS16# Hold from A<23:17>
0
T5A
A<16:12> and SBHE# to 16-Bit Memory Command
18
T5B
A<16:12> and SBHE# to 8-Bit Memory Command
84
T5C
A<15:00> and SBHE# Setup to I/O Command
84
T6
A<16:00> and SBHE# Hold from Command
25
T7
IOCS16# Valid from A <15:00>
25
T8
IOCS16# Hold from A <15:00>
0
T9
IOCHRDY Low from 16-Bit Command (Internal Wait State
Generation)
20
T10
IOCHRDY Active Pulse Width (Memory Cycle) (Internal Wait State
Generation)
123
363
T11
IOCHRDY Active Pulse Width (I/O Cycle) (Internal Wait State
Generation)
63
T12A
A <15:12> to CA <25:12> Valid Delay, Memory Cycles
40
T12B
A <15:12> to CA <25:12> Valid Delay, I/O Cycles
26
T13A
CA <15:12> to Socket I/O CMD Setup
70
T13B
CA <25:12> to Socket Memory CMD Setup
30
T14A
Socket CMD to CE# Hold Time
20
T14B
Socket CMD to REG# Hold Time
0
T15
IOIS16# to IOCS16# Valid Delay
47
T16
IOCS16# Hold from IOIS16# Valid
12
T17
ISA CMD to SKT CMD Valid Delay for 8-Bit Memory, 8/16 I/O
22
T18
ISA Read CMD Falling to Data Output
21
T19
CE#, REG# Setup to Socket CMD Setup
5
T20
ISA CMD Inactive to Socket CMD Inactive Valid Delay
0
20
T21
Socket CMD Inactive to CADR <25:12> Hold Time
20
T22
CA <15:12> Hold from A <15:12> Memory
0
T22
CA<15:12> Hold from A<15:12> I/O
0