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參數(shù)資料
| 型號(hào)： | VSC9142 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH 2.5Gbps Transport Terminating Transceiver |
| 中文描述： | MUX/DEMUX, PBGA320 |
| 封裝： | TBGA-320 |
| 文件頁數(shù)： | 29/30頁 |
| 文件大?。?/td> | 259K |
| 代理商： | VSC9142 |
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G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142
.
4.0 Electrical & Mechanical Data
Page 29
.
Table 1.1
Hardware Signal Definitions (11 of 12)
Pin Label
ALE
Pad
AA12
I/O
I
Type
TTL
Signal Name
CPU Address
Latch Enable
Description
This signal is used to latch internal address bus signals, enabling
access to the device
’
s multiplexed address/data bus. When low
the address bus A[8..0] is latched internally. When high the
internal address bus latches are transparent, which enables the
bus to interface with multiplexed address/data. The ALE signal
has an internal pull-up resistor.
This signal must be asserted to enable internal register read/write
access cycles (active low). The CSB signal is used in conjunction
with the RDB/WRB signals. The CSB signal has an internal pull-
up resistor.
This signal is used for internal register read operations. When
RDB and CSB are both asserted (active low), data in the register
selected by A[8..0] is presented at D[7..0]. The RDB signal has
an internal pull-up resistor.
This signal is used for internal register write operations. When
WRB and CSB are both asserted (active low), data present at
D[7..0] is written to the register selected by A[8..0]. The WRB
signal has an internal pull-up resistor.
This signal is asserted (active low) when an internal interrupt
source is pending and the interrupt is unmasked (enabled). The
INTB signal is de-asserted when the interrupt pending bits have
been cleared. The INTB is an open-drain signal.
This signal is used to performan asynchronous reset of the
device (active low). The device is held in a reset state while the
RSTB signal is low. The signal is Schmtt-trigged with an internal
pull-up resistor. All outputs are tristated when RSTB is asserted.
This bidirectional signal pin provides a means of monitoring PM
Ticks (performance monitoring ticks) and latching internal
performance monitoring counters.
Output:
When configured as an output, this signal is optionally
asserted when the internal PMTICK timer generates a
“
PMTick
”
,
which latches the performance monitoring counters in the device.
Input:
A low-to-high transition optionally latches the performance
monitoring counters in the device.
Note: This pin is configured as an input on reset.
These are general purpose pins that are individually-configurable
as inputs or outputs. They are intended for user-customzable
control and monitoring functions between the VSC9142 and
external devices.
CSB
AD10
I
TTL
CPU Chip Select
(active low)
RDB
AB8
I
TTL
CPU Read Enable
(active low)
WRB
AB10
I
TTL
CPU Write Enable
(active low)
INTB
AA9
O
TTL
CPU Interrupt
(active low)
RSTB
AD3
I
TTL
Chip Reset
(active low)
PMTICK
AB12
I/O
TTL
Performance
Monitoring Tick
M
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
AA20
AB20
AA19
AC20
AB19
AC19
AD19
AB18
I/O
TTL
General Purpose
Input/Output
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