參數(shù)資料
型號： VSC870TX
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： High Performance Serial Backplane Transceiver
中文描述： DUAL LINE TRANSCEIVER, PBGA192
封裝： BGA-192
文件頁數(shù)： 29/40頁
文件大?。?/td> 511K
代理商： VSC870TX
VITESSE
Data Sheet
VSC870
High Performance Serial
Backplane Transceiver
G52190-0, Rev 4.1
01/05/01
Page 29
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
4.0 Direct Mode
4.1 Overview
The transceivers can directly connect to each other without a switch chip to form a simple port to port link. In this
mode, the signal MODE[1] is set LOW and MODE[0] is set HIGH so that the CMU is selected as the transmit clock
and the transceiver word aligns only on the receiving side. The signal LTIME must be set low so the transmitter will
use the CMU as the source of the bit clock. The signal BYPASS should also be set HIGH in Direct Mode to disable
the retransmit and self-routing features used in Packet Mode. The signal CELLSYN is set LOW to disable the cell
synchronization feature. In this configuration, the transceivers will bit and word synchronize to each other. Section
1.5 summarizes these configurations. Also, only data words and command words are used (data word and command
word formats are shown in section 1.2). An example of a three port card system with no switch chip is shown below.
See Application Note 33 for more information.
Figure 13: Switch System using VSC870 Transceiver Only
The transceiver can also be used as a high speed backplane interconnect link. The ability of the transceiver to
perform word and cell synchronization on both transmit and receive sides to a master clock source can help provide a
synchronous system up to the word or cell level. In this mode, the signal BYPASS should be set HIGH to disable
retransmit and self-routing features used in Packet Mode. The signal CELLSYN is set LOW to disable the cell
synchronization feature. In this configuration, the MODE[1:0] signals for transceivers on the switch card are set
LOW to allow these transceivers to be aligned to a common word boundary and act as the master clock source. The
MODE[1:0] signals for transceivers on the port cards are set HIGH to allow these transceivers to be word aligned at
both the transmit and receive sides to the word boundary set by transceivers on the switch card. Multiple transceivers
on a given port card can be word synchronized to each other as described in Application Note 32. An example of
using these transceivers as backplane interconnect links in a parallel switching fabric is shown below.
Port Card
Trans
System
Memory
Trans
Port Card
Trans
System
Memory
Trans
Port Card
Trans
System
Memory
Trans
VSC870
VSC870
VSC870
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