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參數(shù)資料
| 型號(hào)： | VSC870TX |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Performance Serial Backplane Transceiver |
| 中文描述： | DUAL LINE TRANSCEIVER, PBGA192 |
| 封裝： | BGA-192 |
| 文件頁數(shù)： | 23/40頁 |
| 文件大?。?/td> | 511K |
| 代理商： | VSC870TX |
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VITESSE
Data Sheet
VSC870
High Performance Serial
Backplane Transceiver
G52190-0, Rev 4.1
01/05/01
Page 23
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Similar to the Unicast/Multicast Camp-on request, in this mode, after the CRQ word is loaded in the transceiver
parallel interface, it will transmit the CRQ word to the switch and wait for the ACK signal to be returned. During this
time, the user logic should send a maximum of D data words from the parallel interface to the switch. If the
transceiver detects the header word for the next packet at the parallel interface, it stops reading from the FIFO, sets
RTM/TCLK HIGH and starts sending a sequence of CRQ words to the switch.
If user wants to operate in a mode where the CRQ is modified after the early CRQ is submitted to the transceiver,
then the header word should not be loaded into the parallel interface until an ACK is received. After the last data
word of the current packet, a new CRQ can be loaded into the parallel interface of the transceiver. This new CRQ
replaces the current one and is sent to the switch. Since the header word is not seen at the parallel interface, the
repeated sequence of CRQ words is not automatically sent to the switch. Priority can instead be supported by sending
higher priority queue CRQs first and more often then lower priority queue CRQs (see Application Note 31). When
ACK and P[3:0] bits are received, the header word and then data words can then be sent to the transceiver as before.
Figure 7: Multi Queue Transmitter Functional Timing (no early arbitration)
When using early arbitration, the CRQ word is sent to the switch chip D cycles before the end of the current data
packet. If the P[3:0] bits are returned with-in time D, very high bandwidth utilization of the switch can be achieved as
shown in the Figure 8. If the signal RTM/TCLK remains high for too long, the current CRQ can be cancelled by
setting the ABORT signal HIGH. At the switch, the current CRQ will continue to requested a connection until it is
granted or a new CRQ command arrives (this can also be a NULL CRQ to cancel the current request).
After the transceiver receives ACK signal, if DLYEN/CCKIN is LOW, it immediately sets the REN signal HIGH
and sends the header word and data to the switch. If DLYEN/CCKIN is HIGH, it waits for N more cycles before it
sets REN HIGH and sends the header word and data to the switch. During this time, the transceiver sends 4 response
bits (P[3:0]) to the queue selection logic and waits for the selection to take place before sending data to the new
destination. The default value for N is 6 which allows time to receive the P[3:0] bits plus queue processing.
WCLK
TXIN[31:0]
TXTYP[1:0]
REN
ACK/RCLK
CRQ
D0
D1
D2
3
2
Minimum of 9 clock cycles
RTM/TCLK
P0
P1
P2
P3
Time to select data queue
1
HDR
LSB
MSB
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