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參數(shù)資料
| 型號： | VSC870TX |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Performance Serial Backplane Transceiver |
| 中文描述： | DUAL LINE TRANSCEIVER, PBGA192 |
| 封裝： | BGA-192 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 511K |
| 代理商： | VSC870TX |
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VITESSE
Data Sheet
VSC870
High Performance Serial
Backplane Transceiver
Page 20
G52190-0, Rev 4.1
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
If early arbitration is used, the first CRQ word is sent to the switch D cycles before the end of the current packet.
If the ACK is not received before the end of the current packet, the transceiver then operates the same as shown in the
figure above. If the ACK is received before the end of the current packet, the transceiver will set the signal REN low
for one cycle at the end of the current packet after the DLYEN/CCKIN counter has expired. The transceiver then
sends an IDLE to the switch to give it time to reconfigure before the next data packet arrives. The functional timing
diagrams are shown below.
Figure 4: Camp-on with Priority Transmitter Functional Timing (with early arbitration)
In the first CRQ the transceiver sends to the switch, the BRK bit is set. In subsequent CRQ words, this bit is
cleared. The AOA bit is always set in this mode. The user logic can monitor the RTM/TCLK signal, which goes
HIGH after the transceiver receives a new header word, and set LOW when the transceiver sees a new CRQ. In the
case of multicast-with-recast, the RTM/TCLK signal will not go low until it sees a new CRQ during the last recast. If
the RTM/TCLK signal stays HIGH too long, the user logic can abort the CRQ by setting ABORT HIGH.
Because these are camp-on requests, when several multicast CRQs of this type are received by the switch, there
is a potential for a lock-up condition. The chances for lock-up can be reduced by minimizing the number of multicast
requests. Lock-up can be broken by aborting the CRQ after a time-out period determined by the RTM/TCLK signal.
If each port card uses a random time-out period before aborting, there is a higher probability that one of the multicast
requests will be granted. A more efficient multicast method is shown in the next section.
2.3.6 Multicast with Recast Mode (MD[1:0] = 01)
In this mode, after the transceiver is loaded with a single CRQ at the parallel interface, it will send one CRQ
word to the switch and wait for the ACK. During early arbitration, the switch will store this CRQ and arbitrate until
all the outputs requested are granted. During this time it can send a maximum of D (D can be greater than or equal to
zero and is described in section 1.2.3) more data words until the packet header. If the transceiver detects the header
word for the next packet at the parallel interface (see figure 2), it stops reading from the parallel interface by setting
REN LOW. It also sets RTM/TCLK HIGH and starts sending more CRQ words to the switch depending on the value
of CT[2:0]. During this camp-on period, the switch chip will accumulate the available outputs that were requested. If
all connections are granted at some point during this period, the transceiver will receive an ACK from the switch. If
DLYEN/CCKIN is LOW, at this time it sets the REN signal HIGH and sends the header word and data to the switch
WCLK
TXIN[31:0]
TXTYP[1:0]
REN
ACK/RCLK
CRQ
D0
D1
D2
D3
D4
D5
3
1
Min 9 clock cycles
RTM/TCLK
HDR
DX
DX
DX
DX
DX
Last D data words from current packet
IDLE sent to switch for reconfigure time
2
1
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