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參數(shù)資料
| 型號： | VSC8169 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator |
| 中文描述： | MUX/DEMUX, PQFP128 |
| 封裝： | 14 X 20 MM, HEAT SINK, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 191K |
| 代理商： | VSC8169 |
VITESSE
Preliminary Data Sheet
VSC8169
OC-48 (FEC) 16:1 SONET/SDH
MUX with Clock Generator
G52230-0, Rev 3.6
01/02/01
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 2: Enabling FIFO Operation
Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/-
Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/-
Minimum 5 CLK16 cycles
FIFO Mode Operation
Transparent Mode Operation
Holding RESET
“
low
”
for a minimum of 5 CLK16 cycles, then setting
“
high
”
enables FIFO operation.
Holding RESET constantly
“
low
”
bypasses the FIFO for transparent mode operation.
PLL locked to reference clock.
RESET
VSC8169
R2
R2
Z
o
Z
o
R1
R1
V
EE
V
CC
V
CC
R2 + V
EE
R1
R1+R2
= V
TERM
R1
||
R2 = Z
O
Split-end equivalent termination is Z
O
to V
TERM
R1 = 125
R2 = 83
, Zo=50
, V
TERM
= V
CC
-2V
VSC8169
50
V
CC
-2V
Z
O
Z
O
50
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