參數(shù)資料
型號(hào)： VSC8140TW
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
中文描述： TRANSCEIVER, PBGA208
封裝： 23 X 23 MM, THERMALLY ENHANCED, TBGA-208
文件頁數(shù)： 15/34頁
文件大小： 528K
代理商： VSC8140TW
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 15
9/6/00
VITESSE
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
G52251-0, Rev. 4.0
Figure 21: Differential and Single-Ended Input / Output Voltage Measurement
Table 1: Transmitter AC Characteristics
Parameters
Description
Min
Typ
Max
Units
Conditions
T
D
TXCLK16I/TXCLK16O period
Data setup time to the rising edge of
TXCLK16I+
Data hold time after the rising edge
of TXCLK16I+
—
6.4
—
ns
—
T
TXDSU
0.75
—
—
ns
—
T
TXDH
1.0
—
—
ns
—
T
TXDOR
,
T
TXDOF
TXCLK
D
t
TXCLK16R
,
t
TXCLK16F
TXCLK16O
D
TXOUT± rise and fall time
—
—
120
ps
20% to 80% into 100
load.
See Figure 13.
—
Transmit clock duty cycle
40
—
60
%
TXCLK16O± rise and fall times
—
—
250
ps
See Figure 24
TXCLK16O± duty cycle
46
—
53
%
—
Assuming 10% distortion of
TXCLK16O.
—
—
—
TXCLK16I
D
TXCLK16I± duty cycle
35
—
65
%
RCK
D
T
DV
t
DH
Reference clock duty cycle
Parallel data to DINVALID
TXCLKO period
Center of output data eye from
falling edge of TXCLKO
40
—
—
—
60
—
—
%
ns
ps
3 t
D
+ 0.3
401.9
t
PD
-75
—
+75
ps
See Figure 19
Clock Multiplier Performance
T
DJ
Output data jitter
—
—
4
ps
RMS, tested to SONET
specification (12kHz to
20MHz) with 2ps RMS jitter
on REFCLK.
RMS, tested to SONET
specification (12kHz to
20MHz) with 2ps RMS jitter
on REFCLK.
Exceeds SONET/SDH mask
T
CJ
Output clock jitter
—
—
4
ps
Jitter
tol
Jitter tolerance
Tuning Range
—
-100
—
—
—
ppm
+100
Single
Differential
=
α
=
α
a
a
b
b
Differential swing is specified as equal in magnitude to single-ended swing.
* Differential swing
(α
) is specified as | b - a | ( or | a - b | ), as is the single-ended swing.
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